US Patent Application 18233697. THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME simplified abstract

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THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME

Organization Name

Western Digital Technologies, Inc.

Inventor(s)

Mitsuhiro Togo of Yokkaichi (JP)

Fumiaki Toyama of Cupertino CA (US)

Adarsh Rajashekhar of Santa Clara CA (US)

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18233697 titled 'THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME

Simplified Explanation

The patent application describes a semiconductor structure that includes alternating layers of insulating and conductive materials. These layers have stepped surfaces.

  • The semiconductor structure includes alternating layers of insulating and conductive materials.
  • The layers have stepped surfaces.
  • A metal oxide etch stop layer is present on the stepped surfaces.
  • A dielectric material portion is present on the etch stop layer and the stepped surfaces.
  • A memory opening extends vertically through the alternating layers.
  • A memory fill structure is located in the memory opening and contains a memory film and a vertical semiconductor channel.
  • An electrically conductive layer contact via structure extends vertically through the dielectric material portion and the etch stop layer.
  • The via structure contacts one of the conductive layers.


Original Abstract Submitted

A semiconductor structure includes an alternating stack of first insulating layers and first electrically conductive layers, the first alternating stack having first stepped surfaces, at least one first metal oxide etch stop layer overlying and contacting the first stepped surfaces, a first stepped dielectric material portion overlying the at least one first metal oxide etch stop layer and the first stepped surfaces, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and an electrically conductive layer contact via structure vertically extending through the first stepped dielectric material portion and the at least one first metal oxide etch stop layer, and contacting a respective one of the first electrically conductive layers.

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