Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 14th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on March 14th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 166 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (25), H01L23/00 (25), H01L23/528 (24), H01L27/092 (23), H01L23/522 (23)
With keywords such as: layer, structure, semiconductor, dielectric, substrate, device, conductive, gate, die, and region in patent application abstracts.
See the following report for Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 14th, 2024: Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 14th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Ting-Li YANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Di WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Jen LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin Wei KANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B3/00, B81C1/00
Abstract: a micro electro mechanical system (mems) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. the first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
Inventor(s): Peng-Cheng Hong of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jun-Liang Pu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., W.L. Hsu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Kao of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chun Hung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Szu Lee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/44, B29D99/00, C23C14/02, C23C14/20, C23C14/34, C23C18/18, C25D7/04, H01J37/32
Abstract: a sealing article includes a body and a coating layer disposed on at least one surface of the body. the body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. the coating layer comprises at least one metal. the sealing article may be a seal, a gasket, an o-ring, a t-ring or any other suitable product. the sealing article is resistant to ultra-violet (uv) light and plasma, and may be used for sealing a semiconductor processing chamber.
Inventor(s): Yung-Tsun LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-chun YANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tsung LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong NI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/458, B25B11/00
Abstract: a chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. the chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. a size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
Inventor(s): Che Wei YANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Cheng SHIH of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo Liang LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu JIANG of Taipei Ciity (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chan LI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/50, C23C16/40, C23C16/56, H01J37/32
Abstract: some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. the systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.
Inventor(s): Chuan-Chieh Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jung Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): F16M9/00, H01L21/67
Abstract: a support platform is configured to support at least a portion of the weight of an associated semiconductor manufacturing tool, such as a furnace, when the associated semiconductor manufacturing tool is disposed on the support platform. the support platform comprises a base, a support plate disposed on the base and configured to move respective to the base, a brake plate arranged in fixed position respective to the base, and a damper secured to one of the support plate or the brake plate and frictionally engaging a track of the other of the support plate or the brake plate. the track includes a central track portion and inclined track portions extending away from the central track portion on respective first and opposite second sides of the central track portion. the inclined track portions are each inclined with respect to the central track portion.
Inventor(s): Yi-An Lai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/28, H01L21/02
Abstract: an integrated circuit includes a first circuit, formed based on one or more group iii-v compound materials, that is configured to operate with a first voltage range. the integrated circuit includes a second circuit, also formed based on the one or more group iii-v compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. the integrated circuit includes a set of first test terminals connected to the first circuit. the integrated circuit includes a set of second test terminals connected to the second circuit. test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): F21V8/00, G02B6/124, G02B6/42
Abstract: a method includes receiving a workpiece that includes a substrate, a first dielectric layer over the substrate, and an optical layer over the dielectric layer; patterning the optical layer to form a first waveguide and a grating coupler; forming a first opening in the substrate that exposes the first dielectric layer, wherein at least a portion of the first opening is directly over the grating coupler; depositing a metal layer in the first opening; and depositing a second dielectric layer over the metal layer.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/42, H01L23/31, H01L23/538
Abstract: a structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. the electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. the waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. the insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.
Inventor(s): Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/13
Abstract: a method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. a waveguide is formed in the interconnect structure. an optical-engine based interconnect component is bonded to the interconnect structure. the optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.
Inventor(s): Jung-Huei Peng of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wen Cheng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chien Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsun-Hsu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B13/18, G02B7/02, G02B27/10
Abstract: various embodiments of the present disclosure are directed towards a camera module comprising flat lenses. flat lenses have reduced thicknesses compared to other types of lenses, whereby the camera module may have a small size and camera bumps may be omitted or reduced in size on cell phones and the like incorporating the camera module. the flat lenses are configured to focus visible light into a beam of white light, split the beam into sub-beams of red, green, and blue light, and guide the sub-beams respectively to separate image sensors for red, green, and blue light. the image sensors generate images for corresponding colors and the images are combined into a full-color image. optically splitting the beam into the sub-beams and using separate image sensors for the sub-beams allows color filters to be omitted and smaller pixel sensors. this, in turn, allows higher quality imaging.
Inventor(s): Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Ping CHENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Cyonglin Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/82, G03F1/64
Abstract: in a method of cleaning a photo mask, the photo mask is placed on a support such that a pattered surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.
Inventor(s): Ting-Ya CHENG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Han-Lung CHANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Han SHANN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Shuo SU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G02B7/182, H05G2/00
Abstract: a method of controlling an extreme ultraviolet (euv) lithography system is disclosed. the method includes irradiating a target droplet with euv radiation, detecting euv radiation reflected by the target droplet, determining aberration of the detected euv radiation, determining a zernike polynomial corresponding to the aberration, and performing a corrective action to reduce a shift in zernike coefficients of the zernike polynomial.
Inventor(s): Yong-Ting WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu Kai CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F7/20
Abstract: an edge exposure tool may include a lens adjustment device that is capable of automatically adjusting various parameters of an edge exposure lens to account for changes in operating parameters of the edge exposure tool. in some implementations, the edge exposure tool may also include a controller that is capable of determining edge adjustment parameters for the edge exposure lens and exposure control parameters for the edge exposure tool using techniques such as big data mining, machine learning, and neural network processing. the lens adjustment device and the controller are capable of reducing and/or preventing the performance of the edge exposure tool from drifting out of tolerance, which may maintain the operation performance of the edge exposure tool and reduce the likelihood of wafer scratching, and may reduce the down-time of the edge exposure tool that would otherwise be caused by cleaning and calibration of the edge exposure lens.
Inventor(s): Min-Cheng WU of Taitung County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Ju HUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
Abstract: some implementations described herein provide an exposure tool. the exposure tool includes a reticle deformation detector and one or more processors configured to obtain, via the reticle deformation detector, reticle deformation information associated with a reticle during a scanning process for scanning multiple fields of a wafer. the one or more processors determine, based on the reticle deformation information, a deformation of the reticle at multiple times during the scanning process, and perform, based on the deformation of the reticle at the multiple times, one or more adjustments of one or more components of the exposure tool during the scanning process.
Inventor(s): Tai-I Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chen Chu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Wei Liu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Lin Su of Taichung County (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsu Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F7/004, G03F7/09, H01L21/768
Abstract: photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. an interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. the interconnection formation process, among other things, improves a photolithography overlay (ovl) margin since alignment is accomplished on a wider pattern. in addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
Inventor(s): Hung-Chih HSIEH of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsiao WENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H01L21/66
Abstract: an overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. the method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. the second sub-patterns are disposed interleaved between the first sub-patterns. the method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.
Inventor(s): Chih-Yuan YAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yu CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Lung TSOU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, B08B5/00, B08B6/00
Abstract: a particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. the processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. the method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. the method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.
Inventor(s): Po-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Chun TSAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jaw-Juinn HORNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F1/56, H01L23/522
Abstract: in some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. at least one of rows of functional cells includes at least one digital low-dropout voltage regulator (dlvr) cell with the cell height for the row. the dlvr cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. the gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. the four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.
Inventor(s): Tsung-Che Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Ming Fu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsien Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/10, G01R27/02, H03K5/01, H03K19/21
Abstract: an impedance measurement circuit and an operating method thereof are provided. the impedance measurement circuit includes a current source, a voltage controlled oscillator (vco), an operation circuit, and a first delay circuit. the current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. the vco is configured to generate an oscillation signal according to a power voltage on the power rail. the operation circuit is electrically connected to the vco and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. the first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.
Inventor(s): Jheng-Hong Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shing-Huang Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F3/14, G02B27/01, G06F3/01
Abstract: a near eye display system is provided. the near eye display system includes: a frame; a first near eye display mounted on the frame and configured to form a first image directly projected on a first retina of a first eye of a user; a second near eye display mounted on the frame and configured to form a second image directly projected on a second retina of a second eye of the user; and a processing unit located at the frame and configured to generate a display control signal to drive the first near eye display and the second near eye display.
Inventor(s): Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lun Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Jen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F7/76, G06F7/501, H03K19/21
Abstract: a computation apparatus and a computation method with input swapping are provided. the computation apparatus includes a non-zero detection circuit, a swapper policy circuit, a swapper matrix circuit, and an adder tree. the non-zero detection circuit is configured to receive input vectors, inspect non-zero operands in the input vectors and generate a non-zero indicative signal indicating the non-zero operands. the swapper policy circuit is configured to receive and interpret the non-zero indicative signal, and generate multiplexer (mux) selection signals for swapping the non-zero operands according to a set of swapping policies. the swapper matrix circuit is configured to receive the input vectors and the mux selection signal, and perform swapping on operands in the input vectors according to the mux selection signal. the adder tree is configured to receive the input vectors with the swapped operands and perform additions on the input vectors to output a computation result.
Inventor(s): Johnny Chiahao LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsuan HO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wei LAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bing-Hsiu WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/33, G06F30/343
Abstract: a method of generating a first performance-data-library (for a standard-cell-library) includes: for each standard cell that includes multiple gates, sorting the gates into groups including searching for matched ones amongst the gates (matched gates), grouping corresponding matched gates into corresponding multiple member-gates, and (for unmatched ones of the gates having no other matched gate (unmatched gates)), grouping the unmatched gates into corresponding single-member groups; for each standard cell, generating a corresponding first volume of performance data including, for each group, discretely calculating the first volume of performance data, mapping the volume of performance data to the subject gate in the group, and, for each multimember group, mapping the volume of performance data to non-subject gates; and basing the first performance-data-library at least in part on the first volumes of performance data. such mapping is an example of exploiting redundancies in the performance-data to reduce computational burden.
Inventor(s): Kenan Yu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Qingwen Deng of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/3312, G06F30/327, G06F30/392, G06F30/394
Abstract: a method for providing an ic design is disclosed. the method includes receiving and synthesizing a behavioral description of an ic design; generating, based on the synthesized behavioral description, a layout for the ic design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.
Inventor(s): Cheng-YU LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia Chun WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Chung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/398
Abstract: a system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (ic) containing the circuit. each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.
Inventor(s): Yen-Hung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Te HOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/39
Abstract: a partitioning method for partitioning a group of power-ground (pg) cells is disclosed. the method includes: placing at least one out-boundary pg cell on a substrate, wherein power strips of the at least one out-boundary pg cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary pg cell on the substrate, wherein power strips of the at least one in-boundary pg cell are aligned with corresponding power rails on the substrate.
20240086611.BASE LAYOUT CELL_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Shang-Hsuan Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong Zhuang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392
Abstract: systems, methods and devices are provided, which can include an engineering change order (eco) base. a base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (od) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (cmd) pattern; and at least one via region. the base layout cell can be implemented in at least two non-identical functional cells. a first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.
Inventor(s): Po-Hsiang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsingjen WANN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsin KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ming HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/3312, G06F30/367, G06F30/398, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
Abstract: an ic device includes first through third rows of fin field-effect transistors (finfets), wherein the second row is between and adjacent to each of the first and third rows, the finfets of the first row are one of an n-type or p-type, the finfets of the second and third rows are the other of the n-type or p-type, the finfets of the first and third rows include a first total number of fins, and the finfets of the second row include a second total number of fins one greater or fewer than the first total number of fins.
Inventor(s): Yuan-Te Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Yuan Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/31, G06F30/392
Abstract: disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. in one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. in one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. in one aspect, layout verification is performed on the rotated layout component with respect to the base axis.
Inventor(s): Yun-Feng KAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia Yu LING of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06N3/063, H10B41/30
Abstract: a semiconductor device may include a non-volatile memory cell structure that may be formed in a back end region of a semiconductor device. the non-volatile memory cell structure may include a floating gate structure in which a portion of a dielectric layer is included between a gate structure and a word line conductive structure. the separation of the gate structure and the word line conductive structure by the dielectric layer results in the gate structure being a floating gate structure. this enables a charge to be selectively stored on the gate structure, even when power is removed from the word line conductive structure. the non-volatile memory cell structure along with a volatile memory cell structure are provided in the back end region of the semiconductor device, such that caching and long-term storage may be performed in the back end region of the semiconductor device.
Inventor(s): Jaw-Juinn Horng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Chun Tsao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06N3/08, G06N3/04, G11C11/412, G11C11/54
Abstract: one aspect of this description relates to a convolutional neural network (cnn). the cnn includes a memory cell array including a plurality of memory cells. each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. each memory cell is configured to multiply a weight bit and an input bit to generate a product. the at least one first capacitive element is enabled when the product satisfies a predetermined threshold. the cnn includes a reference cell array including a plurality of second capacitive elements. the cnn includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.
Inventor(s): Ku-Feng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06
Abstract: a memory device that includes a first memory cell, a second memory cell and a sense amplifier. the sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. a first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. the gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.
Inventor(s): Sanjeev Kumar Jain of Kanata (CA) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C5/14
Abstract: disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. in one aspect, the memory device includes a memory cell to store data. in one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. in one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.
Inventor(s): Ed McCombs of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/12, G11C5/14, G11C8/08, G11C11/418, G11C11/419
Abstract: a memory device includes memory cells operably connected to column signal lines and to word signal lines. the column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. the column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/22, G11C7/10
Abstract: disclosed herein are related to operating a memory system including memory banks and buffers. each buffer may perform a write process to write data to a corresponding memory bank. in one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. in one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. the first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. the second pointer register may indicate a second entry to be updated. the queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.
Inventor(s): Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd., Sahil Preet Singh of Bangalore (IN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418, G11C11/412
Abstract: a memory device includes a memory bank with a memory cell connected to a local bit line and a word line. a first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. a word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. a first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. a global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. a bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.
Inventor(s): Jau-Yi WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G11C29/08
Abstract: a process is provided to trim pcram cells to have consistent programming curves. initial programming curves of pcram cells are measured. a target programming curve is set up for the pcram cells. each pcram cell is then modulated individually to meet the target programming curve.
20240087646.MEMORY CELL_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Jhon-Jhy Liaw of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C15/04, G11C7/18, H03K19/017
Abstract: memory cells are provided. a memory cell includes a first data storage cell, a second data storage cell and a match cell. the first data storage cell includes a first pull-down transistor, a first pull-up transistor and a first pass-gate transistor. the second data storage cell includes a second pull-down transistor, a second pull-up transistor, and a second pass-gate transistor. the match cell includes a first data transistor and a second data transistor. the first data transistor is electrically connected to the first pull-down transistor, the first pull-up transistor and the first pass-gate transistor. the second data transistor is electrically connected to the second pull-down transistor, the second pull-up transistor and the second pass-gate transistor. the first and second data storage cells and the match cell have the same cell height. the match cell is disposed between the first and second data storage cells.
Inventor(s): Ankita Patidar of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Sandeep Kumar Goel of Dublin CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/44, G01R31/3183, G01R31/3185, G11C29/02, G11C29/10, G11C29/12, G11C29/50
Abstract: a method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
Inventor(s): Shy-Jay Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wilman Tsai of Saratoga CA (US) for taiwan semiconductor manufacturing company, ltd., Ming-Yuan Song of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01F10/32, G11C11/16, H01F41/32, H10B61/00, H10N50/01, H10N50/80, H10N50/85
Abstract: memory stacks, memory devices and method of forming the same are provided. a memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. the magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. the free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
Inventor(s): Wei Ting LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Wei FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32
Abstract: the present disclosure is directed to an in situ closed-loop radio frequency (rf) power management on rf processes such as a plasma etch process, a plasma chemical vapor deposition process, a plasma physical vapor deposition process, a plasma clean process, or the like. an rf power measurement device according to one or more embodiments of the present disclosure assists the in situ closed-loop rf power management on rf processes. in some embodiments, the rf power measurement device includes a coil-shaped current sensor that is wound around the path between an rf generator and a chamber. the coil-shaped current sensor senses the current flowing through this path so that the power of the rf generator may be calibrated without having to separate the rf generator for separate analysis and calibration. the rf power measurement device allows management of rf power in an in situ closed-loop manner.
Inventor(s): Tsung-Jen YANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Zhen CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Li SHIH of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hou SU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/34, C23C14/35
Abstract: in an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
Inventor(s): Chia-Lun CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Jen SHIH of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Sung HUNG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hung HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B08B1/00, B08B1/04, B08B3/02, H01L21/304, H01L21/67, H01L21/687
Abstract: a semiconductor wafer cleaning apparatus is provided. the semiconductor wafer cleaning apparatus includes a spin base, a spindle extending through the spin base, and a clamping member covering the spin base. the spindle includes a mounting part and a supporting part disposed on the mounting part. the mounting part includes an inner projection, the supporting part includes a conical projection, and the conical projection is surrounded by the inner projection. the semiconductor wafer cleaning apparatus further includes a first sealing ring disposed between the spin base and the mounting part.
Inventor(s): Xin-Hua Huang of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Yin Liu of Yonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Hua Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Chih Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lan-Lin Chao of Sindian City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shiung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xiaomeng Chen of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B23K1/00, B23K1/20, B23K20/02, B23K20/233, B23K20/24, H01L23/00
Abstract: a method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
Inventor(s): Yu-Lien HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Cheng LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/311, H01L21/3213
Abstract: a method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (euv) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.
Inventor(s): Chih-Min HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Wen LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ming CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sung YEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/265, H01L21/311, H01L21/3115
Abstract: methods of forming line-end extensions and devices having line-end extensions are provided. in some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. a line-end extension region is formed in the hard mask layer. the line-end extension region extends laterally outward from an end of the first region of the hard mask layer. the line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.
Inventor(s): Chieh-Lung LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yueh YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/304, H01L21/78, H01L23/00, H01L23/31, H01L25/065
Abstract: the present disclosure is directed to methods and devices for devices including multiple die. a wafer is received having a plurality of die and a plurality of scribe lines. a dicing process is performed on the wafer. the dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. in embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. after the dicing, the first die and the second die are mounted on a substrate such as an interposer. the first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.
20240087903.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Feng-Cheng Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shuo-Mao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/304, B28D5/00, H01L21/02, H01L21/48, H01L21/56, H01L21/67, H01L21/683, H01L21/78, H01L23/00, H01L23/28, H01L23/31, H01L23/367, H01L23/498, H01L23/538, H01L25/00, H01L25/10
Abstract: provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. the through via is laterally aside the die. the encapsulant laterally encapsulates the through via and the die. the warpage controlling layer covers the encapsulant and the die. the cap is laterally aside the warpage controlling layer and on the through via. the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.
Inventor(s): Zhen Yu Guan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3105, H01L21/02, H01L21/768
Abstract: in some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. further, a conductive material is formed within the opening of the dielectric layer. a planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. an anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
Inventor(s): Yen-Hao HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Shi WANG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Tun CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Hsin CHI of Longjing Township (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Yuan LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B23K1/00
Abstract: a bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. the pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.
Inventor(s): Yen-Ji CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Shen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B08B9/08, H01L21/02, H01L21/687
Abstract: the disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. the space filling device has an overall density that is higher than the chemicals used to purge the wet bench. as such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. as a result, less purging chemicals are used to fill and bath the wet bench.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/673
Abstract: a frame cassette used for semiconductor processing is provided. the frame cassette includes: a housing; and a plurality of cover cases disposed in the housing. each of the plurality of cover cases is capable of accommodating a frame and includes: a bottom section; a top section parallel to the bottom section; and at least one sidewall extending, in a vertical direction, between and connecting the bottom section and the top section to form an enclosed space.
Inventor(s): Tzu-Chung TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Cheng KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fang-yu LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhih-Yuan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/673, B29C45/72, B29C45/73, B29C45/74, B29C45/78
Abstract: an apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. the apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. the pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. the first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
20240087935.INTERFACE TOOL_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Jyh-Shiou HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong NI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mu-Tsang LIN of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Su-Horng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, F24F9/00, H01L21/687
Abstract: a closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (ffu) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. the gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the ffu inlet. this enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. the closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, H01L21/304, H01L21/67
Abstract: a suction head of a pick-and-place tool for semiconductor device packaging is provided. the suction head includes: a suction unit configured to apply a suction force on a top die and pick the top die; and a warpage-correction mechanism. the warpage-correction mechanism includes a pushing mechanism, and the pushing mechanism includes a plurality of pushing units, each of the plurality of pushing units disposed in a corner region of the suction head. each of the plurality of pushing units includes: a tubular chamber extending vertically relative to a bottom surface of the suction head; and a pusher disposed in the tubular chamber and in air-tight contact with a side wall of the tubular chamber. the pusher is movable vertically and capable of protruding out of the bottom surface of the suction head to push a corner region of the top die and apply a downward force thereon.
Inventor(s): Tsai-Hao HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Cheng KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fang-Yu LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/687, H01L21/66, H01L21/67, H01L21/677, H05F1/00
Abstract: semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (esd) prevention layer is utilized to prevent or reduce esd events from occurring between a semiconductor wafer and one or more components of the apparatuses. in some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. the apparatus further includes an esd prevention layer on the wafer handling structure. the esd prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
Inventor(s): Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Cheng Shiau of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jung Kuo of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En Lin of Xionglin Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chin Liu of Ji-an Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/02, H01L21/311, H01L29/06
Abstract: a semiconductor device and method of manufacture are provided. in some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. the modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.
Inventor(s): Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/033, H01L21/311, H01L21/8234, H01L23/522, H01L23/528, H01L23/532
Abstract: in some embodiments, the present disclosure relates to an integrated chip structure. the integrated chip structure includes a substrate. a gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. a conductive via is disposed on the gate electrode. a liner is arranged along one or more sidewalls of the spacer structure. the conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
Inventor(s): Chun-Hao Kung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chieh Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Feng Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Huang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kei-Wei Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. the method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. the hydrophobic layer is formed on a sidewall surface of the dielectric layer. the method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
Inventor(s): Yu-Hung Lin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsuan Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., You-Hua Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/285, H01L23/485, H01L23/522, H01L23/532
Abstract: a semiconductor device and method of formation are provided. the semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
Inventor(s): Yu-Lien HUANG of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Feng FU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Just LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Sheng LI of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Jung HO of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Bor Chiuan HSIEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Xuan CHEN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Ren WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/768, H01L23/535, H01L27/088, H01L29/08, H01L29/417
Abstract: a method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. the method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. the first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. the gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
Inventor(s): Hung-Ju CHOU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chung Chang of Nantou-County (TW) for taiwan semiconductor manufacturing company, ltd., Jun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Yuan Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Ling Kao of Hsichu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsuan Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/3065, H01L27/092, H01L29/04, H01L29/06, H01L29/10, H01L29/161
Abstract: the embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. the method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. the method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
Inventor(s): Yi-Chao Mao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chuan Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L21/306, H01L21/56
Abstract: an apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. the connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. the timer is configured to generate a clock signal having a plurality of pulses with a time interval. the controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.
Inventor(s): Chu Fu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun Hao Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H10B10/00, H10K59/12, H10K59/127, H10K59/131
Abstract: a driver structure for an organic light-emitting diode (oled) device is provided. the driver structure includes a front-end-of-line (feol) layer; a back-end-of-line (beol) layer disposed on the feol layer; and a customer beol layer disposed on the beol layer. the beol layer includes a customer beol electrical checking structure. the customer beol electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. the customer beol layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. the first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.
Inventor(s): Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsiang Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00, H01L23/31, H01L23/498
Abstract: an integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. the semiconductor substrate has an active surface. the conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. the passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. the conductive vias are respectively located on the contact regions of the conductive pads.
Inventor(s): Yu-Sheng Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hung Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L21/78, H01L23/00, H01L23/498, H01L25/00, H01L25/18
Abstract: an semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. the first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. the second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. the underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. the encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.
Inventor(s): Kai-Fang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ju WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Pin HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ling SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/02, H01L21/48, H01L21/768, H01L23/522, H01L23/532
Abstract: a semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. the dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. the semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hui Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Nan Hung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Fan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/46, H01L23/00, H01L23/31, H01L23/367, H01L23/433
Abstract: a semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. the semiconductor package is disposed on the substrate. the thermal conductive bonding layer is disposed on the semiconductor package. the lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.
Inventor(s): Hung-Ling Shih of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Chuang Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih Kuang Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/308, H01L21/768, H01L23/522
Abstract: the present disclosure, in some embodiments, relates an integrated chip. the integrated chip includes a substrate. a through-substrate-via (tsv) extends through the substrate. a dielectric liner separates the tsv from the substrate. the dielectric liner is along one or more sidewalls of the substrate. the tsv includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. the tsv has a maximum width along the horizontally extending surface.
Inventor(s): Shin-Yi YANG of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/482, H01L23/48, H01L23/528, H01L25/00, H01L25/065, H01L29/06, H01L29/423, H01L29/786
Abstract: embodiments of the present disclosure provide a method for forming a semiconductor package. in one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line. the method also includes forming a first interconnect structure on a first surface of the first integrated circuit die, forming a second interconnect structure on a first surface of the second integrated circuit die, extending a power rail from a second surface of the first integrated circuit die to a first side of a source/drain (s/d) feature, forming one or more power lines through an entire thickness of the first and second integrated circuit dies, respectively, forming a third interconnect structure on the second surface of the first integrated circuit die, and forming a fourth interconnect structure on the second surface of the second integrated circuit die.
Inventor(s): Yuan-Yang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/311, H01L21/768, H01L23/528
Abstract: semiconductor devices, integrated circuits and methods of forming the same are provided. in one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. the first opening, the first dummy plate, and the second dummy plate are vertically aligned.
Inventor(s): Yu-Teng Dai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh Yao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen Tien of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao Liao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
Abstract: some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. a first dielectric layer is disposed laterally between the conductive structures. a spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. an etch stop layer overlies the plurality of conductive structures. the etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.
Inventor(s): Shao-Kuan LEE of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
Abstract: an interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. the first conductive feature is disposed in the dielectric layer. the hard mask layer is disposed on the first conductive feature. the conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. the hard mask layer and the conductive layer are formed by different materials. the capping layer is disposed on the dielectric layer and the conductive layer.
Inventor(s): Ta-Pen GUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Ying CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, G06F30/394
Abstract: a semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. the first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.
Inventor(s): Hsin-Yen Huang of Yonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Fang Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin Teng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-I Bao of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/311, H01L21/768, H01L23/532
Abstract: the present disclosure provides a method for forming an integrated circuit (ic) structure. the method comprises providing a substrate including a conductive feature; forming aluminum (al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. a bottom of the contact trench is on a surface of the al-containing dielectric layer.
Inventor(s): Yi Ching Ong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien Hung Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Haklay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jen Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01F17/00, H01L23/48, H01L23/498
Abstract: a semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. the first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. the second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. the second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
Inventor(s): Chiao-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ho-Hsiang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Yuan LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jin YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ta LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/528, H01L23/58, H01L23/64
Abstract: an integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. the guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. the first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. the third metal layer is above the second metal layer. all metal lines in the second metal layer that are part of the guard ring extend in the first direction.
Inventor(s): Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/31, H01L25/065
Abstract: a semiconductor package includes a die and a plurality of conductive patterns. the die includes a device. the conductive patterns are disposed over the device, wherein the conductive patterns are electrically connected to one another to form a first coil and a second coil surrounding the first coil.
Inventor(s): Chin-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/8234, H01L23/522, H01L27/12
Abstract: provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.
Inventor(s): Chao-Kai Chan of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/8234, H01L23/522, H01L29/06, H01L29/423, H01L29/94
Abstract: a method of forming a semiconductor device is provided. a transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. a first metal via is formed through the first dielectric layer and aside the transistor. a first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. the substrate is thinned from a second side of the substrate. a capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. a second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.
Inventor(s): Kuo-Chiang Ting of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Wei Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/31, H01L25/065
Abstract: a chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Kang Hsieh of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/367, H01L23/40, H01L25/065
Abstract: a semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. the die includes a chamfered corner. the bolt is adjacent to the chamfered corner.
Inventor(s): Jhih-Yu Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/544, H01L21/48, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/538, H01L25/00, H01L25/10
Abstract: a method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. the second redistribution lines are formed using the alignment mark for alignment.
Inventor(s): Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia Yang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hsiang Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/48, H01L23/538, H01L25/065
Abstract: a method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. the first redistribution line is revealed through the via opening. the method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. the conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. the second via is further offset from the second center of the conductive bump.
20240088062.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shen Cheng of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Tsao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Jui Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/498
Abstract: a package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. a coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
Inventor(s): Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/367, H01L23/498
Abstract: a semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. the wiring substrate has a first surface and a second surface opposite to the first surface. the semiconductor component is disposed on the first surface of the wiring substrate. the conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. the bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. the top stiffener is disposed on the first surface of the wiring substrate. the top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
20240088070.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chung-Yi Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Chiang Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ping Wang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H01L25/065, H01Q1/22, H01Q9/04
Abstract: provided is a package structure and a method of forming the same. the package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. the semiconductor package includes a die. the stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. the plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.
Inventor(s): Chia-Feng Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kang-Yi Lien of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ping Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: semiconductor structures and method of forming the same are provided. a semiconductor structure according to the present disclosure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad.
Inventor(s): Chung-Hao Tsai of Huatan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065, H01L25/18
Abstract: packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. in an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.
Inventor(s): Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Ning Shih of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/498, H01L23/538
Abstract: a package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. the redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. the conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. the first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
Inventor(s): Ling-Wei LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hua CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/768, H01L23/31, H01L23/482, H01L23/498, H01L23/522
Abstract: a chip package structure is provided. the chip package structure includes a first substrate. the chip package structure includes a conductive via structure passing through the first substrate. the chip package structure includes a barrier layer over a surface of the first substrate. the chip package structure includes an insulating layer over the barrier layer. the chip package structure includes a conductive pad over the insulating layer. the conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. the chip package structure includes a conductive bump over the conductive pad. the chip package structure includes a second substrate. the chip package structure includes an underfill layer between the first substrate and the second substrate.
Inventor(s): Wensen Hung of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsin Wei of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Pin Hu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/31, H01L23/473, H01L23/498
Abstract: in an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng LIN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/304, H01L23/31, H01L25/00, H01L25/18
Abstract: a method for forming a chip package structure. the method includes bonding first connectors over a front surface of a semiconductor wafer. the method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. the method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. a first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
Inventor(s): Yu-Lun Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kong-Beng Thei of Pao-Shan Villlage (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/522
Abstract: an electronic device and a method for manufacturing the same are provided. the electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. the first metal layer electrically connects the upper electronic structure to the upper connection structure. the second metal layer electrically connects the lower electronic structure to the lower connection structure. the upper connection structure and the lower connection structure are bonded together.
Inventor(s): Xin-Hua Huang of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yeong-Jyh Lin of Caotun Township (TW) for taiwan semiconductor manufacturing company, ltd., Rei-Lin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L23/48, H01L23/528, H01L25/00, H01L27/01
Abstract: various embodiments of the present disclosure are directed towards a three-dimensional (3d) trench capacitor, as well as methods for forming the same. in some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. a first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. a plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. a first through substrate via (tsv) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first tsv to the first and second trench capacitors. the first and second trench capacitors and the electrical coupling therebetween collectively define the 3d trench capacitor.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/48, H01L23/50, H01L23/538, H01L25/10
Abstract: a package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. the plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. the plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.
Inventor(s): Wei-Hung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Min Huang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Jung Hsueh of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Yu Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji Lii of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/78, H01L23/00, H01L23/31, H01L23/498
Abstract: provided are a package structure and a method of forming the same. the method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
Inventor(s): Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L21/48, H01L21/56, H01L25/065, H01L25/10, H01L25/18
Abstract: a method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. the through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. the method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. the electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. the interposer wafer is sawed to separate the package from other packages.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L23/00, H01L25/065, H01L25/18
Abstract: a device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. the device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. the plurality of through vias are disposed adjacent the first die and the second die. the device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. the plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
Inventor(s): Jian-Sing LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L21/8238, H01L27/092, H01L29/423
Abstract: a method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.
Inventor(s): Yu-Tao YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shen CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, G06F30/394, H01L27/088
Abstract: in an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. the drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. the gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. the threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. the threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.
Inventor(s): Yang ZHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liu HAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., XinYong WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., ZeJian CAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L21/265, H01L21/74, H01L21/768, H01L21/8238, H01L23/48, H01L25/00, H01L25/065, H01L27/092
Abstract: a method of manufacturing an ic structure includes configuring each of an n-well and a p-well in a first ic die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming ic devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. forming the ic devices includes forming a pmos transistor in the second or third portion of the n-well and forming an nmos transistor in the second or third portion of the p-well.
Inventor(s): Huaixin XIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yang ZHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L21/8238, H01L23/528, H01L27/092
Abstract: an integrated circuit (ic) device includes at least one circuit having an input and an output, and an output connector electrically coupled to the output. the circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. the output is in a first metal layer. the output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. the second conductive pattern electrically couples the output to the first conductive pattern.
Inventor(s): Yu-Hung YEH of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H02H9/04
Abstract: an apparatus for providing electrostatic discharge (esd) immunity and a method for fabricating the same are disclosed herein. the apparatus comprises a field effect transistor (fet) formed on a semiconductor substrate in a front-end-of-line (feol) layer during an feol process, a metal interconnect layer formed on top of the feol layer during a back-end-of-line (beol) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the fet to a plurality of components formed on the semiconductor substrate, a power delivery network (pdn) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (b-beol) process, and a through substrate resistive component formed between the feol and b-beol layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the fet and second contact is connected, through the pdn, to a power supply rail.
Inventor(s): Tao-Yi HUNG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji CHEN of Wu-Ku (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H02H9/04
Abstract: an electrostatic discharge (esd) protection apparatus and method for fabricating the same are disclosed herein. in some embodiments, the esd protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (esd) circuits patterned in a carrier wafer, where the esd circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient esd events, and where the device wafer is bonded to the carrier wafer.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tuo Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Shiuan Tsair of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L21/8234
Abstract: the present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. the method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.
Inventor(s): Yi-Hsiung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsun Chiu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L23/50, H01L27/02
Abstract: a device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. the device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. a top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. a source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. the source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
Inventor(s): Ji-Cheng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hang Chiu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/28, H01L21/285, H01L21/762, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/51, H01L29/66
Abstract: a gate structure includes a metal layer, a barrier layer, and a work function layer. the barrier layer covers a bottom surface and sidewalls of the metal layer. the barrier layer includes fluorine and silicon, or fluorine and aluminum. the barrier layer is a tri-layered structure. the work function layer surrounds the barrier layer.
Inventor(s): Zhi-Chang Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Ching of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/033, H01L21/8234, H01L29/66, H01L29/78
Abstract: examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. in some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. a first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. a cut feature is formed in the trench. a first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
Inventor(s): XinYong WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cun Cun CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L23/522, H01L23/528
Abstract: an integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. the first terminal-conductor intersects both an active-region structure and a power rail. the second terminal-conductor intersects the active-region structure without intersecting the power rail. the gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. a first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.
Inventor(s): Yi-Ren Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ting Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. the substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. the dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. the gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Heng TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Chao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. a method for manufacturing the semiconductor structure is also disclosed.
Inventor(s): Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chyi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chung Hsiao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jhih-Bin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/28, H01L21/8238, H01L29/06, H01L29/51
Abstract: the present disclosure relates to an integrated circuit (ic) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. in some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. a first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. a boundary dielectric layer is disposed on the isolation structure. a second polysilicon component is disposed on the sacrifice dielectric layer.
Inventor(s): Bo-Yu LAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Hsuan LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L21/8238, H01L29/06, H01L29/66, H01L29/78
Abstract: a semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. the source/drain regions are over a substrate. the gate structure is laterally between the source/drain regions. the first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. the dielectric material is between the first one of the source/drain regions and the void region. the dielectric material has a gradient ratio of a first chemical element to a second chemical element.
Inventor(s): Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ho Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238
Abstract: a semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. the first dielectric layer is disposed on the at least one fin. the second dielectric layer between the at least one fin and the first dielectric layer. a thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.
Inventor(s): Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsien Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kazuaki Hashimoto of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chieh Chiang of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chien Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Cheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kung Chang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: in some embodiments, an image sensor is provided. the image sensor includes a photodetector disposed in a semiconductor substrate. a wave guide filter having a substantially planar upper surface is disposed over the photodetector. the wave guide filter includes a light filter disposed in a light filter grid structure. the light filter includes a first material that is translucent and has a first refractive index. the light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
Inventor(s): Chih Cheng Shih of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsun-Kai Tsao of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Bing Cheng You of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chang Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: trenches in which to form a back side isolation structure for an array of cmos image sensors are formed by a cyclic process that allows the trenches to be kept narrow. each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. the following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. the resulting trenches have a series of vertically spaced nodes. the process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
Inventor(s): Chia-Yu WEI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Ying HUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chi CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L31/0352, H01L31/103
Abstract: an image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. the radiation sensing member is in the semiconductor substrate. an interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. the shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. the color filter layer covers the radiation sensing member.
Inventor(s): Li Chung Yu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Hung Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hao Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02
Abstract: semiconductor structures and methods are provided. an exemplary method includes depositing a first conductive material layer over a substrate, patterning the first conductive material layer to form a first conductor plate over the substrate, forming a first high-k dielectric layer over the first conductor plate, forming a second high-k dielectric layer on the first high-k dielectric layer, forming a third high-k dielectric layer on the second high-k dielectric layer, and forming a second conductor plate over the third high-k dielectric layer and vertically overlapped with the first conductor plate, where a composition of the first high-k dielectric layer is the same as a composition of the third high-k dielectric layer and is different from a composition of the second high-k dielectric layer.
Inventor(s): Fu-Chiang Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/08
Abstract: a capacitance structure comprises a metal nitride layer, such as a titanium nitride (tin) layer, a compositionally graded film formed on a surface of the metal nitride layer by thermal oxidation, and a dielectric layer disposed on the compositionally graded film. a method of manufacturing a capacitance structure includes forming a conductive layer, performing thermal oxidation of a surface of the conductive layer to produce a compositionally graded film on the conductive layer, and forming a dielectric layer on the compositionally graded film.
Inventor(s): Tzu-Ting LIU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tzu CHEN of Taoyuan city (TW) for taiwan semiconductor manufacturing company, ltd., Man-Yun WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ling CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming an interconnect structure over a substrate. the method includes forming a first conductive pad and a mask layer over the interconnect structure. the mask layer covers a top surface of the first conductive pad. the method includes forming a metal oxide layer over a sidewall of the first conductive pad. the method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. the first conductive pad and the second conductive pad are made of different materials.
Inventor(s): Yuan-Sheng Huang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Chen of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/94, H01L29/66
Abstract: various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. the trench capacitor is on a substrate and comprises a plurality of capacitor segments. the capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. the plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. the edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. the greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.
Inventor(s): Hsin-Fu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hao YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/66, H01L29/78
Abstract: a semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. the drift region has a first type conductivity. the anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. a method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.
Inventor(s): Shu-Wen SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Po Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Han Chen of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/66, H01L29/775
Abstract: in a method of manufacturing a semiconductor device, a field effect transistor (fet) having a metal gate structure, a source and a drain over a substrate is formed. a first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. a frontside wiring layer is formed over the first frontside contact. a part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. a first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. a first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
Inventor(s): Su-Hao Liu of Jhongpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Heng Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Lang Wang of Tien-Chung Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L21/265, H01L21/285, H01L21/324, H01L21/768, H01L21/8234, H01L21/8238, H01L27/092, H01L29/161, H01L29/66, H01L29/78
Abstract: a method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. at least a portion of the semiconductor region is molten during the melt anneal.
Inventor(s): Chung-Liang CHENG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I WU of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L21/8238, H01L27/092, H01L29/06, H01L29/66, H01L29/78
Abstract: the structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. the method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (gaa) structures surrounding the first and second nanostructured channel regions, respectively. the forming the first and second gaa structures includes selectively forming an al-based n-type work function metal layer and a si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.
Inventor(s): Yun-Yuan WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsiang HSIAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., I-Chih NI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-I WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L29/08, H01L29/40, H01L29/41
Abstract: a device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. the chalcogenide channel layer is over the substrate. the chalcogenide barrier layer is over the chalcogenide channel layer. a dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. the source/drain contacts are over the chalcogenide channel layer. the gate electrode is over the substrate.
Inventor(s): Ming-Wen HSIAO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen TAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hsin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Jhih KUO of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Feng SHIEH of Yongkang City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/027, H01L21/768, H01L29/417
Abstract: in a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L21/8238, H01L27/088, H01L27/092, H01L29/10, H01L29/40, H01L29/51, H01L29/66
Abstract: methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. in an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ild over the first gate and the second gate; a first contact extending through the ild and coupled to the first source/drain region; and a second contact extending through the ild, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/08, H01L29/10, H01L29/40, H01L29/423, H01L29/78
Abstract: a semiconductor device and a manufacturing method thereof are provided. the gate structure and the source and drain terminals are located in the insulating dielectric layer, and the source and drain terminals are located respectively at both opposite ends of the gate structure. the channel region is sandwiched between the gate structure and the source and drain terminals and surrounds the gate structure. the channel region extends between the source and drain terminals.
Inventor(s): Yu-Ling Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Cheng Li of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ling Shih of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei Liu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tuo Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Shiuan Tsair of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Sheng Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih Kuang Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/265, H01L21/28, H01L21/3213, H01L23/522, H01L23/528, H01L29/40, H01L29/66, H01L29/788
Abstract: various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. in some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. the memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. the erase gate and the word line are elongated in parallel along a row of the memory array. the control gate is elongated along the row and is between and borders the erase gate and the word line. further, the control gate has a pad region protruding towards the erase gate and the word line. because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
Inventor(s): Miin-Jang CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Han YI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsuan LU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/51, H01L29/66, H01L29/78
Abstract: a method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.
Inventor(s): Peng-Wei CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yasutoshi OKUNO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ding-Kang SHIH of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/8238, H01L27/092, H01L29/08, H01L29/165, H01L29/45
Abstract: the structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. a method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. the first metal silicide layer includes a first metal. the first and second conductive regions includes a second metal different from the first metal.
Inventor(s): Hsueh-Chang SUNG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Mu LI of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/3065, H01L21/308, H01L29/04, H01L29/08, H01L29/78
Abstract: a fin structure on a substrate is disclosed. the fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.
Inventor(s): Cheng-Yi PENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chieh YEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ming CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/417, H01L29/423, H01L29/78
Abstract: a semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. the fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. the gate structure extends in a second direction perpendicular to the first direction. the contact material includes a silicon phosphide layer and a metal layer.
Inventor(s): Jiun Shiung WU of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Jie SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/16
Abstract: in a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. the bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. an isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. a dummy gate structure is formed. a source/drain structure is formed. an interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. the dummy gate structure is replaced with a metal gate structure.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wing YEUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66
Abstract: a semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
Inventor(s): Chia-Ling YEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pravanshu MOHANTA of Mumbai (IN) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiang-He XIE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shine LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/778, H01L21/02, H01L21/306, H01L29/20, H01L29/205, H01L29/66
Abstract: disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a high electron mobility transistor (hemt) with a back barrier layer for blocking electron leakage and improve threshold voltage. in one embodiment, a semiconductor device, includes: a gallium nitride (gan) layer; a front barrier layer over the gan layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-dimensional electron gas (2-deg) in the gan layer at a first interface between the gan layer and the front barrier layer; and a back barrier layer in the gan layer, wherein the back barrier layer comprises aluminum nitride (aln).
Inventor(s): Kuei-Ming Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Ming Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/778, H01L21/02, H01L29/66
Abstract: various embodiments of the present application are directed towards a group iii-v device including a rough buffer layer. the rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. the buffer structure causes band bending and formation of a two-dimensional hole gas (2dhg) in the rough buffer layer. the rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. a top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. the carrier scattering reduces carrier mobility and increases resistance at the 2dhg. the increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (pae).
Inventor(s): Wen-Chao Shen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang Chen of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/423, H01L29/66
Abstract: a transistor includes: a substrate; a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section; a first drain and a second drain; a first source and a second source; a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.
Inventor(s): Hung-Chang Sun of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chang Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., TsuChing Yang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66, H10B51/00
Abstract: a transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. the source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. a thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. the channel layer is disposed on the insulating layer, the source region, and the drain region. the ferroelectric layer is disposed over the channel layer. the gate electrode is disposed on the ferroelectric layer.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L29/06, H01L29/24, H01L29/267, H01L29/423, H01L29/66, H01L29/786
Abstract: in a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. in etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.
Inventor(s): Cheng-Yen YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chi WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Chun LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/285, H01L21/3065, H01L21/764, H01L29/06, H01L29/08, H01L29/45, H01L29/66
Abstract: in a method of manufacturing a semiconductor device including a fin fet, a fin structure extending in a first direction is formed over a substrate. an isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. a gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. a fin mask layer is formed on sidewalls of a source/drain region of the fin structure. the source/drain region of the fin structure is recessed. an epitaxial source/drain structure is formed over the recessed fin structure. in the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.
Inventor(s): Chih-Hsuan Tai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chih Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ban-Li Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Cheng Tseng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/0203, H01L31/02, H01L31/024, H01L31/18
Abstract: a semiconductor package is provided. the semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. the second conductive through-via is in contact with the first conductive through-via. the sensor die is located between the second redistribution structure and the heat dissipation substrate. the second redistribution structure has a window allowing a sensing region of the sensor die receiving light. the first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. a method of forming the semiconductor package is also provided.
Inventor(s): Tzu-Heng Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02H9/04, H01L27/02
Abstract: systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. the power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. there may be both a pull-up third diode in the diode string for connection between i/o and vdd and a pull-down third diode between i/o and vss. during an esd event the esd device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. during operational mode the esd device is turned off and does not interfere with circuit operations.
Inventor(s): Garming LIANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Simon CHAI of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jin YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., En-Hsiang YEH of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Sheng CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03F3/21, H01L27/06, H01L27/092, H03F1/02
Abstract: disclosed is an amplifying circuit and method. in one embodiment, an amplifying circuit, includes: a common-gate (cg) amplifier, wherein the cg amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.
Inventor(s): Chin-Hua Wen of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/08, H03F3/45, H03K19/0175, H03K19/0185
Abstract: a post-driver with low voltage operation and electrostatic discharge protection is provided. a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver. the output node is configured to connect to a comparator for impedance calibration of the drive unit. the post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration. the operational amplifier is further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit. the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.
Inventor(s): Yung-Shun Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chow Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/687, H03K19/0175, H03K19/0185
Abstract: a device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. the inverter circuit having an output and including at least two series connected pmos transistors connected, at the output, in series to at least two series connected nmos transistors. the hysteresis control circuit coupled to the output to provide feedback to the at least two series connected pmos transistors and to the at least two series connected nmos transistors. the high-side input level shifter connected to gates of the at least two pmos transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two pmos transistors.
Inventor(s): PO CHUN LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., SHAO-YU WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03L7/07, H03L7/099, H03L7/23
Abstract: a first clock signal is generated from a reference clock signal. a first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. the first clock signal is propagated towards a first component of an integrated circuit through a clock tree. a second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. the second clock signal is provided to the first component.
Inventor(s): Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04L9/32, H04L9/06
Abstract: the present disclosure describes embodiments of a device with memory and a processor. the memory is configured to store integrated circuit (ic) trim and redundancy information. the processor is configured to extract bits from the ic trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. in some embodiments, the memory that stores the ic trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).
Inventor(s): Saman M.I. Adham of Ontario (CA) for taiwan semiconductor manufacturing company, ltd., Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Peter Noel of Ontario (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04L9/32, G06F21/72, G06F21/73, H04L9/08
Abstract: systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (puf) generator. unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.
Inventor(s): Yu-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsi LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ling-Sung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Shan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chan-yu HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G06F30/39, H01L23/528, H01L27/088
Abstract: a semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsun Chiu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, G11C17/16, G11C17/18, H01L23/525
Abstract: a memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. the programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. the reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. the memory device also includes a first and a second gate metals. the first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. the second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.
Inventor(s): Meng-Sheng Chang of Chubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun Chung Su of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsing Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, G11C11/402, G11C17/12, G11C17/16, H01L29/41, H10B20/00, H10B20/25
Abstract: a semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. the semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. the first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Cheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B41/30, H10B41/40
Abstract: a method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. the planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. an etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ren HSIEH of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen CHAN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B41/50, H10B41/40, H10B41/43
Abstract: in a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. in the method, a protrusion of a substrate is formed in the ring structure area. the protrusion protrudes from an isolation insulating layer. a high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. a poly silicon film is formed over the high-k dielectric film. the poly silicon film and the high-k dielectric film are patterned. insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
Inventor(s): Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B43/35, H01L23/522, H10B43/10, H10B43/20
Abstract: a semiconductor structure includes a plurality of memory cells stacked up along a first direction. each of the memory cells include a memory stack, connecting lines, and insulating layers. the memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. the connecting lines are extending along the first direction and covering side surfaces of the memory stack. the insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.
Inventor(s): Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/10, G11C11/22, H10B51/30
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a first dielectric layer over a substrate. a first conductive structure overlies the first dielectric layer. a data storage structure is disposed between the first dielectric layer and the first conductive structure. the data storage structure comprises a data storage layer and a grid structure. the grid structure comprises a plurality of opposing sidewalls spaced across a width of the first conductive structure. the data storage layer is disposed along the plurality of opposing sidewalls. the data storage layer comprises a first material and the grid structure comprises a second material different from the first material.
Inventor(s): Wen-Ling Lu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jun Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Yun Cheng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C11/22, H10B51/20
Abstract: a memory array and an operation method of the memory array are provided. the memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. the ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
Inventor(s): Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/40, G11C11/22, H01L23/522, H10B43/30, H10B43/40, H10B43/50, H10B51/20, H10B51/30, H10B51/50
Abstract: an integrated circuit is provided. the integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. the three-dimensional memory device includes stacking structures separately extending along a column direction. each stacking structure includes a stack of word lines. the stacking structures have first staircase structures at a first side and second staircase structures at a second side. the word lines extend to steps of the first and second staircase structures. the first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
Inventor(s): Chung-Liang CHENG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/20, H01L23/522, H01L23/528, H01L29/423, H10B51/10, H10B51/20, H10B53/00, H10B53/10
Abstract: a ferroelectric memory cell (feram) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. the transistor and its gate contacts are formed on a front side of the substrate. a carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
Inventor(s): William J. Gallagher of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shy-Jay Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Ming Yuan Song of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H10N52/01, H10N52/80
Abstract: various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. a lower via underlies the memory cell. the lower via is laterally offset from the memory cell by a lateral distance. a first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. the first conductive layer continuously extends along the lateral distance. a second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. a bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.
Inventor(s): Chih-Ming Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N30/853, H10N30/00, H10N30/076, H10N30/082, H10N30/50, H10N30/87
Abstract: a piezoelectric device including a substrate, a metal-insulator-metal element, a hydrogen blocking layer, a passivation layer, a first contact terminal and a second contact terminal is provided. the metal-insulator-metal element is disposed on the substrate. the hydrogen blocking layer is disposed on the metal-insulator-metal element. the passivation layer covers the hydrogen blocking layer and the metal-insulator-metal element. the first contact terminal is electrically connected to the metal-insulator-metal element. the second contact terminal is electrically connected to the metal-insulator-metal element.
Inventor(s): Chang-Lin YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hua HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10B61/00, H10N50/80
Abstract: a method for fabricating magnetoresistive random-access memory cells (mram) on a substrate is provided. the substrate is formed with a magnetic tunneling junction (mtj) layer thereon. when the mtj layer is etched to form the mram cells, there may be metal components deposited on a surface of the mram cells and between the mram cells. the metal components are then removed by chemical reaction. however, the removal of the metal components may form extra substances on the substrate. a further etching process is then performed to remove the extra substances by physical etching.
Inventor(s): Ming-Che Ku of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cho Wang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Tsun Chung Tu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiunyu Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Huang Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H01F10/32, H01F41/34, H01L21/768, H01L23/522, H01L23/528, H10B61/00, H10N50/01
Abstract: the present disclosure, in some embodiments, relates to an integrated chip. the integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. the memory device includes a data storage structure disposed between a bottom electrode and a top electrode. a bottom electrode via couples the bottom electrode to a lower interconnect. a top electrode via couples the top electrode to an upper interconnect. a bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.
Inventor(s): Jun-Yao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cho WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01
Abstract: the present disclosure relates to a magneto-resistive random access memory (mram) cell having an extended upper electrode, and a method of formation. in some embodiments, the mram cell has a magnetic tunnel junction (mtj) arranged over a conductive lower electrode. a conductive upper electrode is arranged over the magnetic tunnel junction. below the conductive lower electrode is a first conductive via structure in a first dielectric layer. below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. a dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.
Inventor(s): Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10N70/20
Abstract: provided are a memory cell and a method of forming the same. the memory cell includes a bottom electrode, a top electrode, and a storage element layer. the storage element layer is disposed between the bottom and top electrodes. an extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. a semiconductor device having the memory cell is also provided.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 14th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B81B3/00
- B81C1/00
- Taiwan semiconductor manufacturing company, ltd.
- C23C16/44
- B29D99/00
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- C23C14/34
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- H10N70/20
