Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 8th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on February 8th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 70 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (19), H01L23/00 (15), H01L29/06 (14), H01L27/092 (11), H01L29/66545 (10)
With keywords such as: structure, layer, semiconductor, substrate, gate, dielectric, forming, fin, device, and conductive in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Allen Timothy Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): A61B5/1495, A61B5/1473
Abstract: a biosensor apparatus comprises a biosensor device and a cover that is configured to attach to the biosensor device. the biosensor device includes a surface section that is disposed above the user's skin and an implantable section that is injected into the user's skin. the implantable section includes a bending detector and sensing circuitry. the sensing circuitry includes one or multiples of a biomarker sensor array, a control biomarker sensor array, a temperature sensor, and/or a biofouling detector.
Inventor(s): Ren-Guan Duan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsiang Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chiun-Da Shiue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kai Hu of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/40, C23C16/455
Abstract: a method includes forming a first coating comprising amorphous rare earth metal-containing oxide on a surface of an article using a first atomic layer deposition (ald) process that includes repeating a process of alumina deposition cycles followed by rare earth metal oxide deposition cycles n times. the method also includes forming a second coating comprising crystalline rare earth metal oxide on the first coating using a second ald process. the method also includes forming a third coating comprising amorphous rare earth metal-containing oxide on the second coating using a third ald process that includes repeating a process of alumina deposition cycles followed by rare earth metal oxide deposition cycles n times. the method also includes forming a fourth coating comprising crystalline rare earth metal oxide on the third coating using a fourth ald process. in some embodiments, a ratio of n to n is between about 100 and about 150.
Inventor(s): Sin-I Du of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sui-An Yen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin Hung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Yu Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01K7/22, H01L23/34, H01L49/02, G01K7/18
Abstract: a semiconductor device includes a first substrate and a first device layer. the first device layer is disposed on the first substrate and includes a first region and a second region of the first device layer. the first device layer includes at least one first device and a sensor aside the at least one first device. the sensor includes a first resistor with a first non-linear temperature resistance curve and a second resistor with a second non-linear temperature resistance curve. a temperature of the sensor is linearly related to a difference between a first resistance of the first resistor at the temperature and a second resistance of the second resistor at the temperature.
20240044837.BIOSENSOR_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsing Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N27/447, G01N27/414, B03C5/00
Abstract: a biosensor system includes an array of biosensors with a plurality of electrodes situated proximate the biosensor. a controller is configured to selectively energize the plurality of electrodes to generate a dep force to selectively position a test sample relative to the array of biosensors.
Inventor(s): Tung-Tsun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N33/543
Abstract: a target material identification method includes the following steps. a bio-sensing integrated circuit having a sensor array is provided. the sensor array is divided into 1-nassays, and the 1-nassays are coated with different probes. a calibration process is performed to obtain 1-npre-test measurement values respectively for the 1-nassays. a sample fluid having the target material therein is provided onto the 1-nassays. a bio-sensing process is performed on the sample fluid to obtain 1-npost-test measurement values respectively for the 1-nassays. the 1-npre-test measurement values are compared with the corresponding 1-npost-test measurement values, so as to determine whether the target material is bind to the probes in each of the 1-nassays. an assay having the target material bind to the probe is marked as a binding assay. the target material is identified based on the probe in the binding assay.
Inventor(s): Allen Timothy Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chuan Tai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N33/543, G01N27/414
Abstract: a biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (box) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (mli) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the mli structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.
Inventor(s): Yen-An Chang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Shih of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R21/06, H03K5/24
Abstract: in some aspects of the present disclosure, a power detection system is disclosed. in some aspects, the power detection system includes a constant-transconductance (gm) reference generator circuit receiving a power supply voltage. in some embodiments, the constant-gm reference generator circuit includes a first current mirror to provide a first reference voltage and a second current mirror to provide a second reference voltage. in some embodiments, the constant-gm reference generator circuit includes a power detection circuit coupled to the first current mirror to receive the first reference voltage. in some embodiments, the power detection circuit is coupled to the second current mirror to receive the second reference voltage. in some embodiments, the power detection is operated to receive the power supply voltage. in some embodiments, the power detection circuit is operated to provide an output voltage having one of two logic states at least based on the second reference voltage and the power supply voltage.
Inventor(s): Chin Yin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lin Lee of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Yu Chou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/26
Abstract: a noise monitoring apparatus includes a row selection circuit, a direct current (dc) cancellation circuit and an amplifier circuit. the row selection circuit selects a row of a dut array to be a selected row during a readout period, wherein the selected row comprises a plurality of selected duts. the dc cancellation circuit is coupled to unselected duts of the dut array during the readout period, generates a dc current signal based on bias current signals from a group of unselected duts and subtract the dc current signal from a first noise signal of the selected dut to generate a second noise signal. the amplifier circuit is coupled to the plurality of selected duts of the selected row during the readout period, and amplifies the second noise signal from each of the selected duts to generate an output signal.
Inventor(s): Hsin-Chang LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Hsun LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-I WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi TSAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Wei SHIH of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
Abstract: a method includes forming a reflective multilayer over a substrate; depositing a first capping layer over the reflective multilayer, wherein the first capping layer is made of a ruthenium-containing material or a chromium-containing material; performing a treatment to the first capping layer to introduce nitrogen or fluorine into the first capping layer; forming an absorption layer over the first capping layer; and patterning the absorption layer.
Inventor(s): Hsin-Chang LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Wei SHIH of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24, G03F1/54, G03F1/80, C23C14/22
Abstract: an extreme ultraviolet (euv) mask includes a substrate, a reflective multilayer stack on the substrate, a diffusion barrier layer, a capping layer and a patterned absorber layer. the reflective multilayer stack comprises alternately stacked first layers and second layers. the diffusion barrier layer is on the reflective multilayer stack. the diffusion barrier layer has a composition different from compositions of the first layers and the second layers. the capping layer is on the diffusion barrier layer. the patterned absorber layer is on the reflective multilayer stack.
Inventor(s): An-Ren Zi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Joy Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/32
Abstract: the present disclosure provides a method for lithography patterning in accordance with some embodiments. the method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.
Inventor(s): Shellin Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Tse Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, H01L21/8234, H01L21/308
Abstract: a method includes receiving an integrated circuit (ic) design layout that includes a design boundary and a pair of design fin patterns having a fin spacing and a fin pitch. the method further includes creating a mandrel mask pattern, which includes determining an edge of the mandrel mask pattern based on a location of the design boundary, the fin spacing, and the fin pitch, and determining a width of the mandrel mask pattern based on the fin spacing and the fin pitch. the method further includes creating a cut mask pattern based on the mandrel mask pattern and the design fin patterns, wherein the cut mask pattern is configured to protect an area of a semiconductor wafer corresponding to the design fin patterns. the method further includes fabricating a mandrel mask having the mandrel mask pattern and fabricating a cut mask having the cut mask pattern.
20240046968.SENSE AMPLIFIER_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chia-Fu Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hon-Jarn Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Der Chih of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06
Abstract: a sense amplifier is provided. a first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. a first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. the first invertor is cross coupled with the second invertor at a first node and a second node. a pre-charge circuit is connected to the first node and the second node. a first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. a signal level detector circuit is connected to the second pull up transistor. the signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
Inventor(s): Po-Sheng WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, H01L27/11, G11C11/419
Abstract: a memory device in an integrated circuit is provided, including an input/output (i/o) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the i/o circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the i/o circuit. a first width of the first pair of data lines is different from a second width of the second pair of data lines.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wen WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4094, G11C7/12, G11C11/4096, G11C5/06, G11C11/419, H01L21/48, H10B10/00
Abstract: a semiconductor memory device includes: a local write bit (lwb) line; a local write bit_bar (lwb_bar) line; a global write bit (gwb) line; a global write bit_bar (gwbl_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the lwb and lwb_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.
Inventor(s): Yuan Chih LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Cheng WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/3213, G03F7/16, G03F7/20
Abstract: a method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, exposing the photoresist layer to an euv radiation, developing the photoresist layer to form a patterned photoresist, forming a coating layer on the patterned photoresist, and after forming the coating layer on the patterned photoresist, etching the substrate using a combination of the coating layer and the patterned photoresist as an etching mask.
Inventor(s): Yu-Tien SHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kai YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ming CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Hui CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting CHIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/02, H01L29/66, H01L21/3213, H01L21/28
Abstract: a method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.
Inventor(s): Wei-Ming Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hung Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng Tai of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/308, H01L21/311, H01L23/00
Abstract: a method includes forming an etching mask over a first wafer. the etching mask covers an inner portion of the first wafer. a wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. the edge portion forms a full ring encircling the inner portion of the first wafer. the method further includes removing the etching mask, and bonding the first wafer to a second wafer.
Inventor(s): Meng-Han LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ren HSIEH of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen CHAN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3105, H01L21/308, H01L21/762, H10B41/30
Abstract: an integrated circuit device includes a substrate, an isolation feature, a memory cell, and a semiconductor device. the substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. the isolation feature is in the transition region. a top surface of the isolation feature has a first portion and a second portion lower than the first portion, the second portion of the top surface of the isolation feature is between the cell region and the first portion of the top surface of the isolation feature, and a bottom surface of the isolation feature has a step height directly below the second portion of the top surface of the isolation feature. the is memory cell over the cell region of the substrate. the semiconductor device is over the peripheral region of the substrate.
Inventor(s): Chia-Ching Lee of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Hsuan Tsai of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Tai Wang of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chen Liang Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuo Hui Chang of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/68, H01L21/677, H01L21/60
Abstract: a wafer alignment assembly is provided. the wafer alignment assembly includes: a first tapered wall extending in a first horizontal direction; a first spring wall attached to an inner surface of the first tapered wall; a first set of conveyor rollers configured to rotate; a second tapered wall extending in the first horizontal direction, wherein the first tapered wall and the second tapered wall are characterized by a tapered shape that facilitates entry of a wafer assembly; a second spring wall attached to an inner surface of the first tapered wall; and a second set of conveyor rollers configured to rotate.
Inventor(s): Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Hong Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Wei Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Hui Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L21/762
Abstract: semiconductor structures and methods are provided. an exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. the method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.
Inventor(s): Han-Pin CHUNG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tang PENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-I BAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/762, H01L21/02, H01L27/092, H01L29/78, H01L21/8234, H01L29/66
Abstract: a semiconductor structure and a method for forming the same are provided. the method includes forming a first protruding structure and a second protruding structure over a substrate, and forming a first insulation material layer on the first protruding structure and the second protruding structure. the method includes performing a pre-treatment process on the first insulation material layer to form a first treated insulation material layer, and forming a second insulation material layer on the first treated insulation material layer. the method includes performing a first insulation material conversion process on the first treated insulation material layer and the second insulation material layer. the first protruding structure and the second protruding structure are bent toward opposite directions during the first insulation material conversion process.
Inventor(s): Wei-Chung Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L21/285, H01L23/31
Abstract: a semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. the substrate has a through hole formed therethrough. the composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. the routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. the semiconductor die is electrically connected to the routing via. along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.
Inventor(s): Chin-Liang Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yang Yu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L25/065, H01L23/00, H01L21/48
Abstract: a package structure and a manufacturing method thereof are provided. the package structure includes an integrated substrate and a package component. the integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. a lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. the package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.
Inventor(s): Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung Pan of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L25/16, H01L23/00, H01L23/48
Abstract: a semiconductor package includes a first tier and a second tier underlying the first tier and including tivs and third dies. the first tier includes a first redistribution structure and first and second dies disposed side-by-side and separated by a first insulating encapsulation. a surface of the first insulating encapsulation, surfaces of first die connectors of the first die, and truncated spherical surfaces of second die connectors of the second die are level. the first redistribution structure underlies the surfaces of the first insulating encapsulation and the first die connectors and the truncated spherical surfaces of the second die connectors. the third dies disposed below the first redistribution structure are electrically coupled to the first die through the first redistribution structure and laterally covered by a second insulating encapsulation. the tivs penetrate through the second insulating encapsulation and are electrically coupled to the second die through the first redistribution structure.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Han Lee of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L25/065, H01L23/538, H01L23/42, H01L21/48, H01L25/00, H01L23/00
Abstract: in an embodiment, a device includes: a first integrated circuit die including a first device layer and a first front-side interconnect structure, the first front-side interconnect structure including first interconnects interconnecting first devices of the first device layer; a second integrated circuit die including a second device layer and a second front-side interconnect structure, the second front-side interconnect structure including second interconnects interconnecting second devices of the second device layer; and an interposer bonded to a back-side of the first integrated circuit die and to a back-side of the second integrated circuit die, the interposer including a die-to-die interconnect structure, the die-to-die interconnect structure including a pillar, the first integrated circuit die overlapping the pillar.
Inventor(s): Chien-Ying CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/525, G11C17/16, H01L23/48, H10B20/20
Abstract: an integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. the front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. in the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. a word connection line extending in the first direction is directly connected to a gate terminal of the transistor.
Inventor(s): Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tso-Jung CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Shien HSIEH of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ping LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L25/065, H01L21/48
Abstract: a package structure and a formation method are provided. the method includes disposing a first chip structure and a second chip structure over a carrier substrate. the method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. the interconnection structure has multiple dielectric layers and multiple conductive features. one of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. the method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/065, H01L25/00
Abstract: a device includes a substrate, at least one first dielectric layer on the substrate and including a first dielectric constant, at least one second dielectric layer on the at least one first dielectric layer and including a second dielectric constant greater than the first dielectric constant, and a dummy pattern including a first conductive pattern having a first pattern density in the at least one first dielectric layer and a second conductive pattern in the at least one second dielectric layer and comprising a second pattern density. the first pattern density is equal to or greater than the second pattern density.
Inventor(s): Chi-Hui LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Che CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Tai LU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ray LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L23/528, H01L21/78
Abstract: a semiconductor device includes a first circuit area disposed over a substrate and enclosed by a first seal ring structure, a second circuit area disposed over the substrate and enclosed by a second seal ring structure, an internal scribe line disposed between the first circuit area and the second circuit area, and connecting seal structures connecting the first seal ring structure and the second seal ring structures such that a part of the first seal ring structure, a part of the second seal ring structure and the connecting seal structures enclose the internal scribe line.
Inventor(s): Bo-Yu CHIU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wei LEE of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Fu Wei LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chung WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao Chun YANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Yu KU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ji LII of Sinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: a semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. in one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.
Inventor(s): Meng-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao CHUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/065, H01L25/18, H01L25/00, H01L23/538
Abstract: a package structure is provided. the package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conductive line, and a first conductive via structure. the package structure includes an electronic device bonded to the conductive pad. the package structure includes a chip structure bonded to the first end portion of the first conductive via structure. the package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. the first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.
Inventor(s): Neng-Chieh CHANG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao TSAI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Lun LIU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L25/10
Abstract: a semiconductor package structure includes a conductive pad formed over a substrate. the semiconductor package structure also includes a passivation layer formed over the conductive pad. the semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. the semiconductor package structure also includes a first encapsulating material surrounding the first via structure. the semiconductor package structure further includes a redistribution layer structure formed over the first via structure. the first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hui Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Nan Hung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Fan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/48
Abstract: a structure including a first semiconductor die and a second semiconductor die is provided. the first semiconductor die includes a first bonding structure. the first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. the second semiconductor die includes a second bonding structure. the second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. the first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.
Inventor(s): Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Wei Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
Abstract: a method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.
20240047422.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/498, H01L23/31, H01L23/00, H01L23/48
Abstract: a package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. the at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. the insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. the isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. the redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.
Inventor(s): Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kris Lipu Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L25/18, H01L25/00
Abstract: a semiconductor package and a manufacturing method are provided. the semiconductor package includes a first die disposed on and electrically coupled to a first redistribution structure and laterally covered by a first insulating encapsulation, a second die disposed over the first die and laterally covered by a second insulating encapsulation, a second redistribution structure interposed between and electrically coupled to the first and second dies, a third redistribution structure disposed on the second die and opposite to the second redistribution structure, and at least one thermal-dissipating feature embedded in a dielectric layer of the third redistribution structure and electrically isolated from a patterned conductive layer of the third redistribution structure through the dielectric layer. through substrate vias of the first die are physically connected to the second redistribution structure or the first redistribution structure. the thermal-dissipating feature is thermally coupled to a back surface of the second die.
20240047441.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, H01L21/48, H01L23/10, H01L23/04, H01L23/00
Abstract: a package structure is provided. the package structure includes a first package component and a second package component. the second package component includes a substrate and the first package component is mounted to the substrate. the package structure includes a ring structure disposed on the second package component and around the first package component. the ring structure has a first foot and a second foot parallel to the first foot. the width of the first foot is greater than the width of the second foot.
Inventor(s): Mao-Yen Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Cheng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Da Tsai of Chiayi Country (TW) for taiwan semiconductor manufacturing company, ltd., Hsaing-Pin Kuan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Tsao of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Lai of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung Pan of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L23/00, H01R12/57, H01L25/065, H01L25/00
Abstract: a semiconductor package and a manufacturing method thereof are described. the semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. the redistribution circuit structure is disposed on the package. the first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. the first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. the affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. the affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. the affixing blocks join the first and second modules to the redistribution circuit structure.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L27/092, H01L29/06, H01L29/417, H01L21/8238, H01L29/66, H01L21/762
Abstract: semiconductor devices and semiconductor cell arrays are provided herein. in some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. the multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (fet), and a first p-type fet. the mono-fin active region abuts the multi-fin active region. the mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type fet, and a second p-type fet. the isolation feature is parallel to the first and second gate structures.
Inventor(s): Li-Wei CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fu TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L29/06
Abstract: a method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. the method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. the method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. the method further includes trimming the lines into line segments having ends over the isolation structure. the method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
Inventor(s): Shu-Uei Jang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L29/66, H01L29/78, H01L29/06, H01L21/8234
Abstract: a finfet device includes a first fin and a second fin on a substrate, a dielectric fin, a metal gate line, a gate dielectric layer, a gate isolation structure. the dielectric fin is located between the first fin and the second fin. the metal gate line is across the first fin, the dielectric fin and the second fin. the gate dielectric layer is located between the metal gate line and the dielectric fin, between the metal gate line and the first fin, and between the metal gate line and the second fin. the gate isolation structure extends through the first metal gate line and the gate dielectric layer, and landing on the dielectric fin. a top surface of the gate dielectric layer is lower than a top surface of the gate isolation structure.
Inventor(s): Yu-Lung Tung of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Xiaodong Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L27/02, H01L21/8238, H01L23/528, H01L29/417
Abstract: an ic structure includes a first standard cell having a first pfet and a first nfet integrated; a first, second and third gates longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two s/d contacts on two opposite edges of the first gate; a second gate contact landing on the second gate and being adjacent a single s/d contact on one edge of the second gate; and a third gate contact landing on the third gate and being free from any s/d contact. the first, second and third gate contacts span a first dimension d, a second dimension d, and a third dimension d, respectively, along a second direction being orthogonal to the first direction. d is less than d and d is less than d
Inventor(s): Kuo-Cheng CHING of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L29/66, H01L29/78, H01L29/49, H01L29/51, H01L21/308, H01L21/8238, H01L21/28
Abstract: aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. the semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. the first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.
Inventor(s): Chin-Yu LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Ying LIAO of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Su-Yu YEH of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Zen CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Jen TUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Li CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: an image sensor includes a substrate, a grid, and a color filter. the grid is over the substrate. from a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. the color filter extends through the grid structure.
Inventor(s): Hao-Cheng Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jung Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Yun Hou of Jubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/48, H01L23/498, H01L23/31, H01L23/538, H01L21/56, H01L25/10, H01L27/01
Abstract: a method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. the method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. the device die is electrically coupled to the inductor through the redistribution lines.
Inventor(s): Chun-Tsung Kuo of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chyi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L49/02, H01L23/00
Abstract: a fabrication method includes: forming, over a first dielectric layer between a first metal portion and a second metal portion, a thin film resistor (tfr); forming openings in the first dielectric layer over the first metal portion and the second metal portion; and forming a first bond pad in an opening over the first metal portion and a second bond pad in an opening over the second metal portion; wherein the first dielectric layer is disposed between the first bond pad and the second bond pad, the tfr is formed over the first dielectric layer between the first bond pad and the second bond pad, the tfr has an electrical connection at a first end to the first bond pad and an electrical connection at a second end to the second bond pad, and the tfr provides a resistive path between the first bond pad and the second bond path.
Inventor(s): Shu-Hui SU of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Felix YingKit TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Yu-Chi CHANG of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L49/02, H01L21/764, H01L23/522, H01L23/58, H01L21/768
Abstract: various embodiments of the present disclosure provide a semiconductor device structure. the semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature
Inventor(s): Ting-Yeh Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/66, H01L21/28
Abstract: a method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. the method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. the method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L27/118, H01L27/092, H01L21/8234, H01L29/66
Abstract: a method includes doping a substrate to form a first well region and a second well region having a different conductivity type than the first well region; forming a first fin structure upwardly extending above the first well region and a second fin structure upwardly extending above the second well region; forming a first gate electrode surrounding the first fin structure and a second gate electrode surrounding the second fin structure; forming first source/drain regions adjoining the first fin structure and on opposite sides of the first gate electrode and second source/drain regions adjoining the second fin structure on opposite sides of the second gate electrode; forming an isolation line interposing the first and second gate electrodes and laterally between a first one of the first source/drain regions and a first one of the second source/drain regions.
Inventor(s): Cheng-Ming LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hua CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Zhubei Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/66, H01L21/285, H01L29/51
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a gate stack over a substrate. the method includes forming a spacer over first sidewalls of the gate stack using a first precursor. the first precursor includes a first boron- and nitrogen-containing material having a first hexagonal ring structure, the spacer has a plurality of first layers, and each first layer includes boron and nitrogen.
Inventor(s): Chao-Ching CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Sheng CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Syuan HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/78, H01L29/66, H01L21/02, H01L21/8238, H01L27/088, H01L27/092, H01L29/423, H01L21/8234
Abstract: semiconductor structures and method for forming the same are provided. the semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. the semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. the semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. in addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.
Inventor(s): Ssu-Yu Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Wei Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsu-Hui Su of Tapei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsiang Fan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Bin Huang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/786, H01L21/306, H01L29/66
Abstract: fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. for example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.
Inventor(s): Che-Lun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/786, H01L29/06, H01L29/417, H01L21/308, H01L29/66, H01L29/40
Abstract: an integrated circuit (ic) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. the source/drain epitaxial structures are respectively on opposite sides of the gate structure. the front-side interconnection structure is on front-sides of the source/drain epitaxial structures. the backside dielectric layer is on backsides of the source/drain epitaxial structures. the backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.
Inventor(s): Kuo-Chiang Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Hung Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mu-Chi Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/45, H01L29/40
Abstract: a semiconductor device includes a source via having a body portion and a barrier layer surrounding the body portion, and the body portion is in physical contact with the source contact. furthermore, the barrier layer includes at least one sidewall section separating the source via from an adjacent via structure. as such, the via to via leakage may be prevented. overall, by providing a semiconductor device having the above structures, the contact resistance is reduced, and the device performance is further improved.
Inventor(s): Fu-Chiang Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Liang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chen Hsu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/033, H01L21/027, H01L21/768, H01L29/94
Abstract: the present disclosure provides an embodiment of a method. the method includes patterning a substrate to form trenches; etching the substrate, thereby modifying the trenches with round tips; forming a stack including conductive layers and dielectric layers in the trenches, wherein the conductive layers and the dielectric layers alternate with one another within the stack; forming an insulating compressive film in the first trenches, thereby sealing voids in the trenches; and forming conductive plugs connected to the conductive layers, respectively.
Inventor(s): Wei-Ting Chien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775
Abstract: a method of forming a semiconductor device includes: forming semiconductor fin structures over a substrate, where each of the semiconductor fin structures includes a layer stack over a semiconductor fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a capping layer over sidewalls and upper surfaces of the semiconductor fin structures; and forming hybrid fins over isolation regions on opposing sides of the semiconductor fin structures, where forming the hybrid fins includes: forming dielectric fins over the isolation regions; and forming dielectric structures over the dielectric fins, which includes: forming an etch stop layer (esl) over the dielectric fins; doping the esl with a dopant; and forming a first dielectric material over the doped esl.
Inventor(s): Yi-Hsuan HSIAO of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan KU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chang HUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Wei YANG of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming SUN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/78, H01L29/417, H01L27/092, H01L21/8238
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. the semiconductor device structure also includes a first conductive material and a second conductive material disposed over the semiconductor substrate and the first dielectric layer. the semiconductor device structure further includes a second dielectric layer surrounding the first conductive material and the second conductive material and an insulating structure over the semiconductor substrate. the insulating structure is disposed between the first conductive material and the second conductive material. the insulating structure comprises a material different from the first dielectric layer and the second dielectric layer.
Inventor(s): Li-Hui CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L27/11, H01L29/78, H01L21/8238, H01L29/08, H01L27/092
Abstract: a method of forming a semiconductor device includes forming first and second fin structures on a substrate, forming first and second gate stacks crossing the first and second fin structures, respectively, wherein the first fin structure has a first channel region under the first gate stack and a first source/drain region adjacent to the first channel region, and the second fin structure has a second channel region under the second gate stack and a second source/drain region adjacent to the second channel region, performing an ion implantation process to introduce impurities into the second source/drain region to form an implanted region in the second source/drain region, performing an etching process to form first and second recesses in the first and second source/drain regions, respectively, wherein the second recess penetrates through the implanted region, and forming epitaxy structures in the first and second recesses, respectively.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/78, H01L29/08
Abstract: a method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.
Inventor(s): Bo-Huan HSIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Han CHIOU of Taiwan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L29/06, H01L29/78, H01L27/092
Abstract: a method includes forming a semiconductor fin upwardly extending from a substrate; forming a gate strip extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and at opposite sides of the gate strip; forming a gate spacer on a sidewall of the gate strip; forming a film layer on the gate spacer; performing an etching process on the gate strip to break the gate strip into a first gate structure and a second gate structure, the etching process further consuming the gate spacer while remains the film layer; forming an isolation structure interposing the first and second gate structures.
Inventor(s): Hong-Shyang Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/40, H01L29/06, H01L29/10, H01L29/66
Abstract: a semiconductor device includes a first well of a first conductivity type near a surface of a semiconductor substrate, and a second well of a second conductivity type near the surface of the semiconductor substrate. the semiconductor device includes a transistor comprising: (i) a first source/drain region formed in the first well; (ii) a second source/drain region formed in the second well; and (iii) a gate structure formed near the surface of the semiconductor substrate and separated from the second source/drain region at least with a portion of a third well of the second conductive type. the semiconductor device includes an isolation structure formed near the surface of the semiconductor substrate and further separating the second source/drain region from the gate structure. the semiconductor device includes a plurality of field plates formed above at least one of the portion of the third well or the isolation structure.
Inventor(s): Zheng-Long CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/10, H01L29/40, H01L29/66, H01L21/265, H01L21/266, H01L21/324, H01L21/225
Abstract: a semiconductor device includes a substrate, a deep well, a doped region, a gate, and source and drain regions. the deep well is of a first conductivity type in the substrate. the doped region is in the deep well with an impurity of a second conductivity type. the field oxide is over the deep well and has a side interfaced with the doped region. the gate is over the field oxide. the source and drain regions are over the substrate and laterally separated at least in part by the doped region and the field oxide.
Inventor(s): Chih-Tsung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Felix yingkit Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/107
Abstract: a photodetection device and a manufacturing method are provided. the photodetection device includes an absorption structure, a cathode, a charge multiplication region and an anode. the absorption structure is formed in a recess at a surface region of a semiconductor substrate, and configured to receive an incident light. the cathode is formed on a top surface of the absorption structure, and has a first conductive type. the charge multiplication layer is in lateral contact with the absorption structure, and is an intrinsic portion of the semiconductor substrate extending into the semiconductor substrate from a topmost surface of the semiconductor substrate. the anode is in lateral contact with the charge multiplication layer from a side of the charge multiplication region away from the absorption structure, and is a doped region in the semiconductor substrate having a second conductive type complementary to the first conductive type.
Inventor(s): Huaixin XIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liu HAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jing DING of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K5/135, G06F30/392, H03K3/037, H03K17/687, G06F1/04
Abstract: an integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. the first enabling transistor is coupled between the clocking transistor and a first node. the second enabling transistor is coupled between the clocking transistor and a second node. the branch-one transistor is coupled between a first power supply and the first node. the gate terminal of the branch-one transistor is connected to the second node. the branch-two transistor is coupled between the first power supply and the second node. the gate terminal of the branch-two transistor is connected to the first node. each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
Inventor(s): Martin Kinyua of Cedar Park TX (US) for taiwan semiconductor manufacturing company, ltd., Eric Soenen of Austin TX (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03M1/14, H03M1/06, H03M1/16
Abstract: an analog-to-digital converter (adc) includes a first adc stage with a first sub-adc stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. a current mode dac stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. a second adc stage is coupled to the first adc stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. an alignment and digital error correction stage is configured to combine the first and the second digital values.
Inventor(s): Jen-Yuan Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H05K7/20
Abstract: cooling systems for integrated circuit devices are provided. a cooling system according to the present disclosure includes a coolant tank containing a coolant, a cooling coil disposed within the coolant tank, a refrigerant circulating in the cooling coil, and a circulation pump disposed in the coolant tank and configured to circulate the coolant within the coolant tank.
20240049459.EFUSE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, H01L23/525
Abstract: a metal fuse structure may be provided. the metal fuse structure may comprise a first fuse element and a second fuse element. the second fuse element may be adjacent to the first fuse element for a length l. the second fuse element may be spaced apart from first fuse element by a width w.
Inventor(s): Chen-Jun Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sun-Yi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/11568, H01L27/11521, H01L27/1159, H01L27/22, H01L27/24, G11C16/08, G11C11/22, G11C11/16, G11C13/00
Abstract: a memory cell array is provided. the memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. a plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.
Inventor(s): Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsing Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/24, H01L45/00
Abstract: a memory device and a semiconductor die are provided. the memory device includes single-level-cells (slcs) and multi-level-cells (mlcs). each of the slcs and the mlcs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. the first electrode in each of the mlcs is greater in footprint area as compared to the first electrode in each of the slcs.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on February 8th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- A61B5/1495
- A61B5/1473
- Taiwan semiconductor manufacturing company, ltd.
- C23C16/40
- C23C16/455
- G01K7/22
- H01L23/34
- H01L49/02
- G01K7/18
- G01N27/447
- G01N27/414
- B03C5/00
- G01N33/543
- G01R21/06
- H03K5/24
- G01R31/26
- G03F1/24
- G03F1/54
- G03F1/80
- C23C14/22
- G03F7/004
- G03F7/32
- G06F30/392
- H01L21/8234
- H01L21/308
- G11C7/06
- G11C7/10
- H01L27/11
- G11C11/419
- G11C11/4094
- G11C7/12
- G11C11/4096
- G11C5/06
- H01L21/48
- H10B10/00
- H01L21/027
- H01L21/3213
- G03F7/16
- G03F7/20
- H01L21/02
- H01L29/66
- H01L21/28
- H01L21/311
- H01L23/00
- H01L21/3105
- H01L21/762
- H10B41/30
- H01L21/68
- H01L21/677
- H01L21/60
- H01L27/088
- H01L21/8238
- H01L27/092
- H01L29/78
- H01L23/48
- H01L21/768
- H01L21/285
- H01L23/31
- H01L23/498
- H01L25/065
- H01L25/16
- H01L23/538
- H01L23/42
- H01L25/00
- H01L23/525
- G11C17/16
- H10B20/20
- H01L23/58
- H01L23/528
- H01L21/78
- H01L25/18
- H01L21/56
- H01L25/10
- H01L23/10
- H01L23/04
- H01R12/57
- H01L27/02
- H01L29/06
- H01L29/417
- H01L29/49
- H01L29/51
- H01L27/146
- H01L27/01
- H01L21/764
- H01L23/522
- H01L27/118
- H01L29/423
- H01L29/786
- H01L21/306
- H01L29/40
- H01L29/45
- H01L21/033
- H01L29/94
- H01L29/775
- H01L29/08
- H01L29/10
- H01L21/265
- H01L21/266
- H01L21/324
- H01L21/225
- H01L31/107
- H03K5/135
- H03K3/037
- H03K17/687
- G06F1/04
- H03M1/14
- H03M1/06
- H03M1/16
- H05K7/20
- H01L27/11568
- H01L27/11521
- H01L27/1159
- H01L27/22
- H01L27/24
- G11C16/08
- G11C11/22
- G11C11/16
- G11C13/00
- H01L45/00
- H01L29/66545
