Micron Technology, Inc. patent applications on February 8th, 2024
Patent Applications by Micron Technology, Inc. on February 8th, 2024
Micron Technology, Inc.: 42 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), H01L27/11582 (8), H01L23/528 (7), G06F3/0679 (7), G06F3/0659 (6)
With keywords such as: memory, device, data, material, semiconductor, conductive, structure, read, surface, and command in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Alexander Mokhnatyuk of South Pasadena CA (US) for micron technology, inc.
IPC Code(s): G03H1/00, H01L27/146, H04N23/10, H04N23/84, G03H1/04
Abstract: a method, apparatus, and system that provides a holographic layer as a micro-lens array and/or a color filter array in an imager. the method of writing the holographic layer results in overlapping areas in the hologram for corresponding adjacent pixels in the imager which increases collection of light at the pixels, thereby increasing quantum efficiency.
Inventor(s): Li-Te Chang of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Charles See Yeung Kwong of Redwood City CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Seungjune Jeon of Santa Clara CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06N20/00
Abstract: a processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. in response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. a machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. a media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
20240045596.LOW-POWER BOOT-UP FOR MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Reshmi Basu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., David Aaron Palmer of Boise ID (US) for micron technology, inc., Luca Porzio of Casalnuovo (IT) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for low-power boot-up for memory systems are described. a memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Ching-Huang LU of Fremont CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: in some implementations, a memory device may detect a read command associated with reading data stored by the memory device. the memory device may determine whether the read command is from a host device in communication with the memory device. the memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. the memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.
Inventor(s): Zhuo Chen of Boise ID (US) for micron technology, inc., Beth R. Cook of Boise ID (US) for micron technology, inc., Dale W. Collins of Boise ID (US) for micron technology, inc., Muralikrishnan Balakrishnan of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for self-aligned techniques for forming connections in a memory device are described. a redistribution layer (rdl) for coupling an electrode of a capacitor of a memory cell with a corresponding selector device may be fabricated at a same time or stage as the electrode, using self-aligned techniques. when forming portions of a memory cell, a cavity for the electrode may be etched, and a portion of the rdl that extends from the electrode cavity to a corresponding selector device may also be selectively etched. the resulting cavities may be filled with an electrode material, which may form the electrode and couple the electrode to the corresponding selector device. the resulting memory device may support implementation of a staggered configuration for memory cells, and may include electrodes that share a crystalline structure with one or more corresponding portions of an rdl.
Inventor(s): Michael Sheperek of Longmont CO (US) for micron technology, inc., Larry J. Koudele of Erie CO (US) for micron technology, inc., Bruce A. Liikanen of Berthoud CO (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc.
IPC Code(s): G06F3/06, G01K7/02, G01K3/00, G01K3/04, G01K1/02
Abstract: a system includes a memory device and a processing device, operatively coupled to the memory device. in some embodiments, the processing device accesses a matrix of threshold voltage offset bins, where a first dimension of the matrix is temperature and a second dimension of the matrix is a temporal voltage shift (tvs) amount. the processing device measures a temperature value based on a reference temperature value for a block family. the processing device measures a tvs value of a voltage level within one or more memory cell of the block family. the processing device retrieves, from the matrix, a threshold voltage offset bin based on the reference temperature value and the tvs value and reads data from any page of the block family via application of a threshold voltage offset, specified by the threshold voltage offset bin, to a base read level voltage.
Inventor(s): Curtis Egan of Brighton CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for coding for quad-level memory cells having a replacement gate configuration are described. data may be received for storage in a memory device that includes a memory array with memory cells having a replacement gate configuration. the data may be assigned to a plurality of different types of pages within a memory cell of the memory cells using a unit-distance code. the data may be written to the plurality of pages of the different types within the memory cell based at least in part on assigning the data to the plurality of pages of the different types within the memory cell using the unit-distance code to distribute the pages in a way to avoid inconsistent voltage shifting across the plurality of pages of different types.
20240045612.RATING-BASED MAPPING OF DATA TO MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Carla L. Christensen of Boise ID (US) for micron technology, inc., Gangotree Chakma of San Jose CA (US) for micron technology, inc., Yingqi Zheng of San Jose CA (US) for micron technology, inc., Yunfei Xu of Santa Clara CA (US) for micron technology, inc., Bhumika Chhabra of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for rating-based mapping of data to memory are described. a memory system may determine a first rating for a set of data selected for writing to a memory system. the memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. the memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Sanjay Subbarao of Irvine CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include receiving a write command including user data. the write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. temporary parity data is generated using the first and second user data portions. the temporary parity data and the first and second user data portions are stored in a buffer. portions of the first and second block are programmed with two programming passes. the first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. the temporary parity data is maintained in the buffer until a second programming pass of the first and second block.
20240045617.ADDRESS VERIFICATION AT A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for address verification at a memory system are described. a memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. for example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. the memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. the address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.
Inventor(s): Matthew B. Leslie of Boise ID (US) for micron technology, inc., Timothy M. Hollis of Boise ID (US) for micron technology, inc., Roy E. Greeff of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/04, G06F13/16
Abstract: a memory subsystem architecture that includes two register clock driver (rcd) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. in a two rcd device implementation, first and second rcd devices may contemporaneously provide first subchannel c/a information and second subchannel c/a information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. because each of the first and second rcd devices operate responsive to the common clock signal, operation of the first and second rcd devices may be synchronized such that all subchannel driver circuits drive respective subchannel c/a information contemporaneously.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/30, G06F9/448, G06F15/78, G06F9/38
Abstract: representative apparatus, method, and system embodiments are disclosed for configurable computing. a representative system includes an asynchronous packet network having a plurality of data transmission lines forming a data path transmitting operand data; a synchronous mesh communication network; a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the asynchronous packet network and to the synchronous mesh communication network, each configurable circuit of the plurality of configurable circuits adapted to perform a plurality of computations; each configurable circuit of the plurality of configurable circuits comprising: a memory storing operand data; and an execution or write mask generator adapted to generate an execution mask or a write mask identifying valid bits or bytes transmitted on the data path or stored in the memory for a current or next computation.
Inventor(s): Lei Zhang of Singapore (SG) for micron technology, inc., Francis Chee Khai Chew of Singapore (SG) for micron technology, inc., Michael Miller of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06N5/02
Abstract: a processing device in a memory sub-system identifies a set of parameters associated with one or more errors detected with respect to a memory device of a memory sub-system. a vector representing the set of parameters is generated. based on the vector, a classification value corresponding to the one or more errors is generated. based on the classification value, a set of error recovery operations is selected from a plurality of sets of error recovery operations, and the set of error recovery operations is executed.
Inventor(s): Zhengang Chen of San Jose CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06
Abstract: a method may comprise detecting an error associated with accessing a set of data items. the set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. in response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on rain redundancy metadata. in response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on lun redundancy metadata. in response to determining that the set of data items comprises rain redundancy metadata, a first data reconstruction process is performed to regenerate the rain redundancy metadata based at least in part on one or more sets of codewords.
20240045762.QUEUE MANAGEMENT FOR A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Reshmi Basu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F3/06
Abstract: methods, systems, and devices for queue management for a memory system are described. the memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. the memory system may receive a command and identify an expected latency for performing an error control operation on the command. the memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
Abstract: methods, systems, and devices for weighted valid address count (vac) for garbage collection are described. a memory system may select a data block for reorganization (e.g., garbage collection) based on a weighted vac. the memory system may include valid data units associated with various types of data and may track respective quantities of valid data units associated with respective types of data. the memory system may determine the weighted vac of the data block based on a weighted average of the respective quantities of valid data units, where respective weights may be applied to the respective quantities of valid data units. the memory system may select the data block based on the weighted vac, which may be different than a total vac of the data block, and may perform a reorganization procedure on the selected data block.
Inventor(s): Chiara Cerafogli of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F16/9535, G06F16/9538
Abstract: processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. the processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.
Inventor(s): Abhishek Chaurasia of Redmond WA (US) for micron technology, inc., Shakti Nagnath Wadekar of West Lafayette IN (US) for micron technology, inc.
IPC Code(s): G06V10/82, G06V10/80, G06V10/77, G06V10/764, G06V10/26
Abstract: a system for optimizing a vision transformer block for use with mobile vision transformers utilized for tasks, such as image classification, segmentation, and objected detection is disclosed. the system includes incorporating a 1�1 convolutional layer in place of a 3�3 convolutional layer in a fusion block of the vision transformer block to reduce constraints on scaling neural network size. additionally, the system includes fusing local and global representations in the fusion block of the vision transformer block instead of fusing input features and global representations. furthermore, the system includes fusing input features in the fusion block by adding the input features to the output of the 1�1 convolutional layer of the fusion block. moreover, the system includes substituting a 3�3 convolutional layer in the local representation block of the vision transformer block with a depthwise-separable 3�3 convolutional layer. the optimized transformer block enhances image classification, segmentation, and object detection.
Inventor(s): Luigi Pilolli of L’Aquila (IT) for micron technology, inc., Guan Wang of San Jose CA (US) for micron technology, inc., Rosario D’Esposito of Avezzano (IT) for micron technology, inc., Andrew Proescholdt of Rancho Cordova CA (US) for micron technology, inc., Lucia Botticchio of Pescina (IT) for micron technology, inc., Luca Di Loreto of Capistrello (IT) for micron technology, inc.
IPC Code(s): G11C11/4076, G11C11/4099, G11C11/4096
Abstract: operations include generating a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of a memory device, comparing the voltage level to a reference voltage level to generate a comparison result, generating based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and adjusting the duty cycle associated with digital signal based on the command.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/4076
Abstract: a memory subsystem receives a first read command and a second read command. responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. the memory subsystem executes the first read command using the reverse read trim setting. the memory subsystem executes the second read command using the forward read trim setting.
20240046987.SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Harutaka Honda of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): G11C14/00, G11C8/14, H01L27/02, H01L27/108
Abstract: an apparatus includes: a first memory mat; a second memory mat adjacent to the first memory mat; a peripheral circuit between the first memory mat and the second memory mat, the peripheral circuit defining a first boundary to the first memory mat and a second boundary to the second memory mat and including a plurality of wiring patterns in a wiring layer; and at least one dummy pattern in the wiring layer arranged on or along the first boundary.
Inventor(s): Jiewei Chen of Meridian ID (US) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L27/11565, H01L27/1157, H01L27/11582
Abstract: a method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. the lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. an upper stack is formed directly above the lower stack. the upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. the upper stack comprises upper channel-material strings of select-gate transistors. individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. the upper and lower first tiers are conductive at least in a finished-circuitry construction. the upper and lower second tiers are insulative and comprise insulative material. an insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. the insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. other embodiments, including structure, are disclosed.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Juane LI of Milpitas CA (US) for micron technology, inc., Sead ZILDZIC, JR. of Folsom CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/34
Abstract: implementations described herein relate to a memory device with a fast write mode to mitigate power loss. in some implementations, the memory device may detect a condition associated with power supplied to the memory device. the memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. the memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. the memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.
20240046998.3D NAND MEMORY WITH BUILT-IN CAPACITOR_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/30
Abstract: apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. the set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. the set of memory components include a slit portion dividing the first and second memory blocks. the slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/12, G11C7/10
Abstract: implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may identify a first data mask inversion (dmi) bit of the memory device that is associated with a first rank of the memory device and a second dmi bit of the memory device that is associated with a second rank of the memory device. the memory device may set the first dmi bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. the memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first dmi bit to the first value.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/683, H01L23/31, H01L23/00, H01L25/065, H01L21/56
Abstract: methods of making a semiconductor device assembly are provided. the methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. at least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. the method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.
20240047285.SEMICONDUCTOR DEVICES WITH FLEXIBLE SPACER_simplified_abstract_(micron technology, inc.)
Inventor(s): Faxing Che of Singapore (SG) for micron technology, inc., Wei Yu of Singapore (SG) for micron technology, inc., Yeow Chon Ong of Singapore (SG) for micron technology, inc., Shin Yueh Yang of Taichung (TW) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/14, H01L21/52
Abstract: a semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. the spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. the spacer carries the semiconductor die. the flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. the embedded support structure provides strength needed to support the semiconductor die during assembly.
Inventor(s): Rutuparna Narulkar of Boise ID (US) for micron technology, inc., Chandra Tiwari of Boise ID (US) for micron technology, inc., Dmitry Mikulik of Meridian ID (US) for micron technology, inc., Erica A. Ellingson of Boise ID (US) for micron technology, inc., Yucheng Wang of Boise ID (US) for micron technology, inc., Mathew Thomas of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/522, H01L23/535, H01L27/11556, H01L27/11582
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a cavity comprising a flight of stairs. a lining has a specific resistance of at least 1�10ohm�m at 20� c. atop treads of the stairs of the flight of stairs. individual of the treads comprise conducting material of one of the conductive tiers. the lining comprises at least one of (a), (b), (c), and (d), where: (a): m1m2ohaving a specific resistance of at least 1�10ohm�m at 20� c. and where m1 and m2 are each a different one of hf, zr, al, ta, sc, and y; “z” is greater than zero; and at least one of “x” and “y” is greater than zero; (b) bcohaving a specific resistance of at least 1�10ohm�m at 20� c. and where each of “t” and “v” is greater than zero (c): bchaving a specific resistance of at least 1�10ohm�m at 20� c. and where each of “r” and “s” is greater than zero; and (d): bcnhaving a specific resistance of at least 1�10ohm�m at 20� c. and where each of “k” and “p” is greater than zero. insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. methods are disclosed.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L23/535, H01L27/11582
Abstract: methods, systems, and devices for support structures for three dimensional memory arrays are described. for example, a portion of a memory die may formed at least in part from a stack of material layers deposited over a substrate, and the memory die may include a set of access lines in a staircase arrangement over the stack. at least a portion of the stack of material layers between the staircase arrangement and the substrate may be configured to be continuous, or uninterrupted, which may result in fewer physical discontinuities in the stack of material layers below the staircase arrangement. in some examples, at least a portion of the stack of material layers (e.g., conductive portions) in such a region may be electrically isolated from other portions of the memory die, which may support aspects of structural support while limiting electrical interaction with the other portions of the memory die.
Inventor(s): Walter L. Moden of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/56, H01L21/308, H01L23/532, H01L23/495, H01L27/105
Abstract: semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. a representative semiconductor device comprises a substrate including a plurality of conductive contacts and a mask material having a surface. the mask material includes (a) a first recess formed in the surface having a first depth and (b) a second recess formed in the surface having a second depth greater than the first depth. an exposed portion of each of the conductive contacts is exposed from the mask material in the second recess. the semiconductor device further comprises a semiconductor die including a lower surface having bond pads, and the lower surface is positioned in the first recess. the semiconductor device further comprises a plurality of conductive features electrically coupling individual ones of the bond pads to corresponding ones of the exposed portions of the conductive contacts.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L29/24, G11C5/06, H10B12/00
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. the memory cell includes a first transistor and a second transistor. the first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. the second transistor includes a second region electrically coupled to the charge storage structure and the data line. the ground connection is coupled to the first region of the first transistor. the conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.
Inventor(s): Yiping Wang of Boise ID (US) for micron technology, inc., Jiewei Chen of Meridian ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01L27/11556, H01L27/11582
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the stack extends from a memory-array region into a stair-step region. the stair-step region comprises a cavity comprising a flight of stairs. the first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. a lining is formed in and that less-than-fills the cavity atop treads of the stairs. individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. the lining that is atop the treads is replaced with at least one of metal material, polysilicon, or sige and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the sige. conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the sige. individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. other embodiments, including structure, are disclosed.
20240047396.BONDED SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Thiagarajan Raman of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/065
Abstract: this document discloses techniques, apparatuses, and systems for a bonded semiconductor device. a semiconductor assembly is described that includes a first semiconductor die having a first surface and a second semiconductor die having a second surface. a first electrical contact coupled to the first semiconductor die protrudes from the first surface and couples, through a solder joint, to a second electrical contact that couples to the second semiconductor die and protrudes from the second surface. a first non-conductive bonding structure protrudes from the first surface and couples to a second non-conductive bonding structure that protrudes from the second surface.
Inventor(s): Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/304
Abstract: a semiconductor device assembly is provided. the assembly includes an outer semiconductor device which has an active surface and a back surface. the back surface includes a cut that extends to a depth between the active surface and the back surface, and uncut regions on opposing sides of the cut. the assembly further includes an inner semiconductor device disposed within the cut of the outer semiconductor device.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/78, H01L23/00
Abstract: semiconductor dies and devices, such as memory dies and devices, and associated systems and methods, are disclosed herein. a representative semiconductor die comprises a substrate including a first surface, a second surface opposite the first surface, a perimeter, and a recess formed into the first surface adjacent to the perimeter. the recess has a depth in a direction extending between the first surface and the second surface. the semiconductor die further comprises a first bonding structure on the first surface and a second bonding structure on the second surface. the first bonding structure has a thickness, and the depth is at least ten times greater than the thickness. the recess can facilitate mechanical debonding of the semiconductor die during a manufacturing process that includes stacking the semiconductor die within a semiconductor device package.
20240047428.MEMORY DEVICES AND ELECTRONIC SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/528, H01L23/532, H01L23/00, H01L25/00
Abstract: a microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. the first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. the memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.
20240047450.METHODS OF FORMING MICROELECTRONIC DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/18, H01L25/00, H01L23/00, H10B12/00
Abstract: a method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. an additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. the additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. the memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. microelectronic devices, electronic systems, and additional methods are also described.
Inventor(s): Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc., Martin F. Schubert of Mountain View CA (US) for micron technology, inc.
IPC Code(s): H01L33/62, H01L33/00, H01L33/06, H01L33/08, H01L33/32, H01L33/50, H01L33/58
Abstract: vertical solid-state transducers (“ssts”) having backside contacts are disclosed herein. an sst in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the sst, a second semiconductor material at a second side of the sst opposite the first side, and an active region between the first and second semiconductor materials. the sst can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. a portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. a conductive carrier substrate can be disposed on the dielectric material. an isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.
Inventor(s): Chiara Cerafogli of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): H04N21/2668, H04N21/258, H04N21/234, H04N21/25, H04N21/845
Abstract: processing logic receives an indication of at least one of content preferences or contextual information associated with a request to view a media content stream and controls one or more parameters of the media content stream according to the at least one of the content preferences or contextual information to create a personalized media content stream. the processing logic further provides the personalized media content stream to a user device.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Dong Wang of Singapore (SG) for micron technology, inc., Rui Zhang of Boise ID (US) for micron technology, inc., Da Xing of Singapore (SG) for micron technology, inc., Xiao Li of Boise ID (US) for micron technology, inc., Pei Qiong Cheung of Singapore (SG) for micron technology, inc., Xiao Zeng of Singapore (SG) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/40, H10B43/40
Abstract: some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. the conductive structures include a first stack over a metal-containing region. a semiconductor material is within the first stack. a second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. cell-material-pillars are within the memory array region. the cell-material-pillars include channel material. the semiconductor material directly contacts the channel material. conductive post structures are within the other region. some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. others of the conductive post structures are live posts electrically coupled with cmos circuitry. some embodiments include methods of forming assemblies.
Inventor(s): Ashonita A. CHAVAN of Boise ID (US) for micron technology, inc., Aysha Siddique SHANTA of Boise ID (US) for micron technology, inc., Aditi P. KULKARNI of Broomfield CO (US) for micron technology, inc.
IPC Code(s): H01L27/11507
Abstract: implementations described herein relate to various structures, integrated assemblies, and memory devices. in some implementations, an integrated assembly includes a cell plate, a pillar that includes a bottom electrode and a leaker device on top of the bottom electrode, and a top electrode. the top electrode includes a first top electrode portion and a second top electrode portion. the first top electrode portion is separated from the bottom electrode by the leaker device. the second top electrode portion is separated from the bottom electrode and the leaker device by an insulator. the leaker device is configured to discharge excess charge from the bottom electrode to the cell plate via the first top electrode portion.
Inventor(s): Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Mattia Robustelli of Milano (IT) for micron technology, inc.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
Abstract: methods and devices based on the use of dopant-modulated etching are described. during fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. after etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. a multi-deck memory device may also be formed using dopant-modulated etching. memory storage elements on different memory decks may have different taper profiles and different doping gradients.
Micron Technology, Inc. patent applications on February 8th, 2024
- Micron Technology, Inc.
- G03H1/00
- H01L27/146
- H04N23/10
- H04N23/84
- G03H1/04
- Micron technology, inc.
- G06F3/06
- G06N20/00
- G01K7/02
- G01K3/00
- G01K3/04
- G01K1/02
- G06F1/04
- G06F13/16
- G06F9/30
- G06F9/448
- G06F15/78
- G06F9/38
- G06F11/07
- G06N5/02
- G06F11/10
- G06F12/02
- G06F16/9535
- G06F16/9538
- G06V10/82
- G06V10/80
- G06V10/77
- G06V10/764
- G06V10/26
- G11C11/4076
- G11C11/4099
- G11C11/4096
- G11C11/4074
- G11C14/00
- G11C8/14
- H01L27/02
- H01L27/108
- G11C16/04
- H01L27/11565
- H01L27/1157
- H01L27/11582
- G11C16/10
- G11C16/34
- G11C16/30
- G11C29/46
- G11C29/12
- G11C7/10
- H01L21/683
- H01L23/31
- H01L23/00
- H01L25/065
- H01L21/56
- H01L23/14
- H01L21/52
- H01L23/522
- H01L23/535
- H01L27/11556
- H01L23/528
- H01L21/308
- H01L23/532
- H01L23/495
- H01L27/105
- H01L29/24
- G11C5/06
- H10B12/00
- H01L21/304
- H01L21/78
- H01L25/00
- H01L25/18
- H01L33/62
- H01L33/00
- H01L33/06
- H01L33/08
- H01L33/32
- H01L33/50
- H01L33/58
- H04N21/2668
- H04N21/258
- H04N21/234
- H04N21/25
- H04N21/845
- H10B43/27
- H10B41/27
- H10B41/40
- H10B43/40
- H01L27/11507
- H10N70/00
- H10B63/00
- H10N70/20
- G06F3/0679
- G06F3/0659
