SEARCH RESULTS for assignor:"LICHTENAU, CEDRIC"

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(X0) 16017188: LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS

(A1) 20180306858: LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS

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(X0) 14987848: LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS

(A1) 20170192054: LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS

(B2) 1: LOGIC BUILT IN SELF TEST CIRCUITRY FOR USE IN AN INTEGRATED CIRCUIT WITH SCAN CHAINS

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(X0) 15967812: OVERFLOW DETECTION FOR SIGN-MAGNITUDE ADDERS

(A1) 20180253282: OVERFLOW DETECTION FOR SIGN-MAGNITUDE ADDERS

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(X0) 15372867: OVERFLOW DETECTION FOR SIGN-MAGNITUDE ADDERS

(A1) 20180165063: OVERFLOW DETECTION FOR SIGN-MAGNITUDE ADDERS

(B2) 1: OVERFLOW DETECTION FOR SIGN-MAGNITUDE ADDERS

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(X0) 15454113: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

(A1) 20170176531: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

(B2) 1: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

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(X0) 15454160: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

(A1) 20170176532: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

(B2) 1: REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST

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(X0) 15282077: CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS

(A1) 20180095767: CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS

(B2) 9: CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS

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(X0) 15840033: DECIMAL AND BINARY FLOATING POINT ROUNDING

(A1) 20180101358: DECIMAL AND BINARY FLOATING POINT ROUNDING

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(X0) 14803710: CHECKING ARITHMETIC COMPUTATIONS

(A1) 20160019028: CHECKING ARITHMETIC COMPUTATIONS

(B2) 9: CHECKING ARITHMETIC COMPUTATIONS

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(X0) 15822261: CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS

(A1) 20180095768: CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS

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(X0) 15425164: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

(A1) 20170261557: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

(B2) 9: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

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(X0) 15063953: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

(A1) 20170261556: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

(B2) 9: CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY

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(X0) 15063772: BYPASSING AN ENCODED LATCH ON A CHIP DURING A TEST-PATTERN SCAN

(A1) 20170261550: BYPASSING AN ENCODED LATCH ON A CHIP DURING A TEST-PATTERN SCAN

(B2) 9: BYPASSING AN ENCODED LATCH ON A CHIP DURING A TEST-PATTERN SCAN

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(X0) 14922352: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS

(A1) 20160092375: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS

(B2) 9: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS

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(X0) 15354151: DECIMAL AND BINARY FLOATING POINT ROUNDING

(A1) 20170068517: DECIMAL AND BINARY FLOATING POINT ROUNDING

(B2) 9: DECIMAL AND BINARY FLOATING POINT ROUNDING

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(X0) 14501196: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS

(A1) 20160092387: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS

(B2) 9: DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS