US Patent Application 18448897. SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY simplified abstract

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SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Zequn Huang of Hefei City (CN)

SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18448897 titled 'SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY

Simplified Explanation

The patent application describes a signal sampling circuit that includes several components to process command signals and chip select signals.

  • The signal input circuit determines the command signal and chip select signal to be processed.
  • The clock processing circuit performs two-stage sampling and logical operations on the chip select signal to obtain a chip select clock signal.
  • The chip select control circuit samples the chip select signal to obtain an intermediate chip select signal and performs logical operations on it, along with the command signal, to obtain a command decoding signal.
  • The output sampling circuit samples the command decoding signal according to the chip select clock signal to obtain a target command signal.

The innovation in this patent application lies in the design and configuration of the signal sampling circuit, which allows for efficient processing and decoding of command signals based on chip select signals.


Original Abstract Submitted

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.

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