US Patent Application 18448143. SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT simplified abstract

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SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Fong-Yuan Chang of Hsinchu (TW)

Chin-Chou Liu of Hsinchu (TW)

Hui-Zhong Zhuang of Hsinchu (TW)

Meng-Kai Hsu of Hsinchu (TW)

Pin-Dai Sue of Hsinchu (TW)

Po-Hsiang Huang of Hsinchu (TW)

Yi-Kan Cheng of Hsinchu (TW)

Chi-Yu Lu of Hsinchu (TW)

Jung-Chou Tsai of Hsinchu (TW)

SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18448143 titled 'SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT

Simplified Explanation

The patent application describes a system for generating a layout diagram of a wire routing arrangement.

  • The system includes a processor and memory with computer program code.
  • The system places a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern.
  • It determines if the first candidate location violates a design rule by creating a non-circular group of cut patterns in a row.
  • The non-circular group consists of two cut patterns that abut the same boundary of the row, and the total number of cut patterns in the group is even.
  • If the design rule is violated, the system temporarily prevents placement of the cut pattern until a correction is made to avoid the violation.


Original Abstract Submitted

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.