US Patent Application 18447680. TRANSISTOR SPACER STRUCTURES simplified abstract
Contents
TRANSISTOR SPACER STRUCTURES
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chansyun David Yang of Shinchu (TW)
TRANSISTOR SPACER STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447680 titled 'TRANSISTOR SPACER STRUCTURES
Simplified Explanation
- The patent application describes a method for reducing parasitic capacitance between a transistor's gate structures and the source/drain contacts. - The method involves forming a gate structure on a substrate and a spacer stack on the sidewall surfaces of the gate structure. - The spacer stack includes an inner spacer layer, a sacrificial spacer layer, and an outer spacer layer. - The sacrificial spacer layer is removed to create an opening between the inner and outer spacer layers. - A polymer material is deposited on the top surfaces of the inner and outer spacer layers. - The top sidewall surfaces of the inner and outer spacer layers are etched to create a tapered top portion. - A seal material is then deposited. - The resulting gate spacer structures with air-gaps help reduce parasitic capacitance.
Original Abstract Submitted
The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.
