US Patent Application 18447489. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Wei-Chih Kao of Taipei (TW)]]

[[Category:Hsin-Che Chiang of Taipei City (TW)]]

[[Category:Chun-Sheng Liang of Puyan Township (TW)]]

[[Category:Kuo-Hua Pan of Hsinchu City (TW)]]

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447489 titled 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

Simplified Explanation

- The patent application describes a dummy fin for a semiconductor device. - The dummy fin has a low dielectric constant outer shell and a high dielectric constant inner core. - The high dielectric constant core fills any voids in the low dielectric constant outer shell, improving electrical isolation and device performance. - This dummy fin design avoids bending issues that can degrade AC performance in other types of dummy fins. - The processes for forming these dummy fins are compatible with other fin field effect transistor (finFET) formation processes. - The integration of these dummy fins helps minimize polishing issues, etch back issues, and other semiconductor processing issues.

Original Abstract Submitted

A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.