US Patent Application 18447455. DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS simplified abstract

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DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yi-Lin Chuang of Hsinchu (TW)

Shih-Yao Lin of Hsinchu (TW)

Szu-ju Huang of Hsinchu (TW)

Yin-An Chen of Hsinchu (TW)

Shih Feng Hong of Hsinchu (TW)

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447455 titled 'DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

Simplified Explanation

- This patent application describes a system and method for predicting design rule check (DRC) violations in a placement layout before routing is performed. - The system includes DRC violation prediction circuitry that receives placement data associated with the layout. - The circuitry inspects the placement data, which may include data for different regions of the layout. - The circuitry predicts whether there would be systematic DRC violations in the layout if it is routed. - The goal is to identify potential violations early in the design process to avoid costly rework later on.


Original Abstract Submitted

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.