US Patent Application 18447416. SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Ting-Chen Tseng of Hsinchu (TW)
Sih-Hao Liao of New Taipei City (TW)
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447416 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME
Simplified Explanation
The abstract describes a package and method for an integrated circuit die. The package includes an integrated circuit die with two different sloped facets on its sidewall. The die is surrounded by an encapsulant and an insulating layer. The upper surface of the die is lower than the upper surface of the encapsulant, and the sidewall of the insulating layer is coplanar with one of the facets.
- Package and method for an integrated circuit die
- Integrated circuit die has two different sloped facets on its sidewall
- Die is surrounded by an encapsulant and an insulating layer
- Upper surface of the die is lower than the upper surface of the encapsulant
- Sidewall of the insulating layer is coplanar with one of the facets
Original Abstract Submitted
A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
