US Patent Application 18446818. Systems and Methods for Controlling Power Management Operations in a Memory Device simplified abstract

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Systems and Methods for Controlling Power Management Operations in a Memory Device

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Sanjeev Kumar Jain of Ottawa (CA)

Sahil Preet Singh of Amritsar (IN)

Atul Katoch of Kanata (CA)

Systems and Methods for Controlling Power Management Operations in a Memory Device - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446818 titled 'Systems and Methods for Controlling Power Management Operations in a Memory Device

Simplified Explanation

This patent application describes a system and method for controlling the wake-up operation of a memory circuit. The memory circuit includes a memory array with multiple memory cells, as well as various logic circuitry and switching circuitry.

  • The first logic circuitry generates a pre-charge signal for a specific memory cell in response to a sleep signal.
  • The first switching circuitry provides power to the bit line of the first memory cell based on the pre-charge signal.
  • The first latch circuitry receives the sleep signal and the pre-charge signal, and generates a delayed sleep signal.
  • The second logic circuitry generates a pre-charge signal for another memory cell in response to the delayed sleep signal.
  • The second switching circuitry provides power to the bit line of the second memory cell based on the pre-charge signal.

Overall, this innovation allows for efficient control of the wake-up operation in a memory circuit, ensuring that the necessary power is provided to the appropriate memory cells based on the sleep signal.


Original Abstract Submitted

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal. The second logic circuitry may be configured to generate a second bit line pre-charge signal for a second memory cell of the plurality of memory cells, where the second bit line pre-charge signal is generated in response to the delayed sleep signal. The second switching circuitry may be configured to provide power to one or more bit line of the second memory cell in response to the second bit line pre-charge signal.

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