US Patent Application 18446771. INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME simplified abstract

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INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Yu-Jung Chang of Hsinchu (TW)

Chin-Chang Hsu of Hsinchu (TW)

Hsien-Hsin Sean Lee of Duluth GA (US)

Wen-Ju Yang of Hsinchu (TW)

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446771 titled 'INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The patent application describes a system for manufacturing integrated circuits.

  • The system includes a computer readable medium and a processor.
  • The processor executes instructions for placing gate layout patterns on a first layout level.
  • The processor also generates a cut feature layout pattern that extends in a specific direction.
  • The set of gate layout patterns corresponds to fabricating gate structures of the integrated circuit.
  • The cut feature layout pattern overlaps each gate layout pattern at the same position in another direction.
  • The cut feature layout pattern identifies the location of a removed portion of a gate structure.


Original Abstract Submitted

A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.

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