US Patent Application 18446748. SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Jiun Yi Wu of Zhongli City (TW)

Chen-Hua Yu of Hsinchu (TW)

SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446748 titled 'SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE

Simplified Explanation

The patent application describes a structure that includes a core substrate and a redistribution structure.

  • The structure has multiple redistribution layers, each consisting of a dielectric layer and a metallization layer.
  • The structure also includes a local interconnect component embedded in one of the redistribution layers.
  • The local interconnect component has a substrate, an interconnect structure, and bond pads.
  • The bond pads of the local interconnect component physically contact a metallization layer of another redistribution layer.
  • The metallization layer of the other redistribution layer contains conductive vias.
  • The dielectric layer of the first redistribution layer encapsulates the local interconnect component.


Original Abstract Submitted

In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

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