US Patent Application 18446665. SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME simplified abstract
SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Bwo-Ning Chen of Keelung City (TW)
Xusheng Wu of Hsinchu City (TW)
Pin-Ju Liang of Changhua County (TW)
Chang-Miao Liu of Hsinchu (TW)
Shih-Hao Lin of Hsinchu City (TW)
SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18446665 titled 'SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME
Simplified Explanation
The patent application describes a semiconductor device and a method for manufacturing it.
- The semiconductor device includes stacked semiconductor layers over a substrate.
- The semiconductor layers are separated from each other and stacked vertically.
- An isolation structure is present around the bottom of the semiconductor stack, separating active regions.
- A metal gate structure is located over the channel region of the semiconductor stack and wraps around each of the semiconductor layers.
- A gate spacer is present over the source/drain region of the semiconductor stack and along the sidewalls of the metal gate structure.
- An inner spacer is located over the source/drain region of the semiconductor stack and along the lower portions of the metal gate structure, wrapping around the edge portions of each semiconductor layer.
Original Abstract Submitted
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.
