US Patent Application 18446557. EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR simplified abstract

EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Kuan-Liang Liu of Pingtung City (TW)]]

[[Category:Sheng-Chau Chen of Tainan City (TW)]]

[[Category:Chung-Liang Cheng of Changhua County (TW)]]

[[Category:Chia-Shiung Tsai of Hsin-Chu (TW)]]

[[Category:Yeong-Jyh Lin of Caotun Township (TW)]]

[[Category:Pinyen Lin of Rochester NY (US)]]

[[Category:Huang-Lin Chao of Hillsboro OR (US)]]

EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446557 titled 'EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR

Simplified Explanation

The patent application describes an integrated chip that includes two transistors arranged over a substrate.

• The first transistor has channel structures between source/drain regions, a gate electrode, and a protection layer.
• The second transistor also has channel structures between source/drain regions, a gate electrode, and a protection layer.
• The chip also includes an interconnect structure and a contact plug structure.

Original Abstract Submitted

In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.