US Patent Application 18366771. Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same simplified abstract

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Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Hsien-Wei Chen of Hsinchu (TW)

Ming-Fa Chen of Taichung City (TW)

Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18366771 titled 'Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same

Simplified Explanation

The patent application describes a semiconductor device with multiple layers and interconnects. Here are the key points:

  • The device has a substrate as its base.
  • A first dielectric layer is placed over the substrate.
  • A first interconnect is embedded within the first dielectric layer.
  • A second dielectric layer is added on top of the first dielectric layer and the first interconnect.
  • A conductive via is created, passing through the first and second dielectric layers and the substrate.
  • The top surface of the conductive via is aligned with the top surface of the second dielectric layer.
  • A third dielectric layer is applied over the second dielectric layer and the conductive via.
  • A fourth dielectric layer is added on top of the third dielectric layer.
  • A second interconnect is formed within the fourth dielectric layer.
  • The second interconnect physically connects with the first interconnect by passing through the third and second dielectric layers.


Original Abstract Submitted

A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.

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