US Patent Application 18366740. THREE-DIMENSIONAL MEMORY DEVICE AND METHOD simplified abstract
Contents
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Katherine H. Chiang of New Taipei City (TW)
Chung-Te Lin of Tainan City (TW)
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18366740 titled 'THREE-DIMENSIONAL MEMORY DEVICE AND METHOD
Simplified Explanation
- The patent application describes a method for manufacturing 3D memory array devices. - The method involves etching two trenches in a multilayer stack, which consists of alternating dielectric layers and sacrificial layers. - A word line is formed by replacing a sacrificial layer with a conductive material. - A first transistor is formed in the first trench, which includes a first channel isolation structure. - A cut channel plug is formed in the second trench, aligned with the channel isolation structure. - A second transistor is formed adjacent to the cut channel plug in the second trench. - The word line is electrically connected to both the first and second transistors.
Original Abstract Submitted
3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.
