US Patent Application 18366297. Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same simplified abstract
Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Tzu-Chung Wang of Hsinchu (TW)
Chao-Ching Cheng of Hsinchu (TW)
Tzu-Chiang Chen of Hsinchu (TW)
Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same - A simplified explanation of the abstract
This abstract first appeared for US patent application 18366297 titled 'Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same
Simplified Explanation
- The patent application describes techniques for creating a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. - The semiconductor structure includes a substrate and multiple separate semiconductor nanowire strips stacked vertically over the substrate. - A semiconductor epitaxy region is adjacent to and laterally contacts each of the nanowire strips. - A gate structure is positioned at least partially over the nanowire strips. - A dielectric structure is positioned laterally between the semiconductor epitaxy region and the gate structure. - The dielectric structure has a hat-shaped profile. - The innovation aims to improve the performance and efficiency of gate-all-around FET devices by creating a low resistance junction between the source/drain region and the nanowire channel region. - The hat-shaped profile of the dielectric structure helps in achieving this low resistance junction.
Original Abstract Submitted
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
