US Patent Application 18365362. INTEGRATED CIRCUIT PACKAGE AND METHOD simplified abstract

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INTEGRATED CIRCUIT PACKAGE AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Wen-Chih Chiou of Zhunan Township (TW)

Chen-Hua Yu of Hsinchu (TW)

Shih Ting Lin of Taipei City (TW)

Szu-Wei Lu of Hsinchu (TW)

INTEGRATED CIRCUIT PACKAGE AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18365362 titled 'INTEGRATED CIRCUIT PACKAGE AND METHOD

Simplified Explanation

The patent application describes a device that includes an interposer, two integrated circuit devices, a buffer layer, and an encapsulant.

  • The interposer is a component that connects the integrated circuit devices.
  • The first and second integrated circuit devices are bonded to the interposer using dielectric-to-dielectric and metal-to-metal bonds.
  • A buffer layer surrounds the integrated circuit devices and is made of a stress reduction material with a lower Young's modulus.
  • An encapsulant surrounds the buffer layer, integrated circuit devices, and interposer, and is made of a molding material with a higher Young's modulus.
  • The purpose of the buffer layer is to reduce stress on the integrated circuit devices.
  • The encapsulant provides protection and stability to the overall device.
  • The difference in Young's modulus between the buffer layer and the encapsulant ensures that the stress reduction material absorbs more stress than the molding material.


Original Abstract Submitted

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

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