US Patent Application 18364697. SIDEWALL SPACER STRUCTURE FOR MEMORY CELL simplified abstract

SIDEWALL SPACER STRUCTURE FOR MEMORY CELL

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Yao-Wen Chang of Taipei (TW)]]

[[Category:Chung-Chiang Min of Zhubei City (TW)]]

[[Category:Harry-Hak-Lay Chuang of Zhubei City (TW)]]

[[Category:Hung Cho Wang of Taipei (TW)]]

[[Category:Tsung-Hsueh Yang of Taichung City (TW)]]

[[Category:Yuan-Tai Tseng of Zhubei City (TW)]]

[[Category:Sheng-Huang Huang of Hsinchu City (TW)]]

[[Category:Chia-Hua Lin of New Taipei City (TW)]]

SIDEWALL SPACER STRUCTURE FOR MEMORY CELL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18364697 titled 'SIDEWALL SPACER STRUCTURE FOR MEMORY CELL

Simplified Explanation

The patent application describes a method for forming an integrated chip with a memory cell stack and sidewall spacer structure.

• The method involves forming a memory cell stack with a top electrode on a substrate.
• A sidewall spacer structure is then formed around the memory cell stack, consisting of a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer in between.
• A dielectric structure is formed over the sidewall spacer structure.
• A first etch process is performed to define an opening above the top electrode, by etching the dielectric structure and the second sidewall spacer layer.
• The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process.
• Finally, a top electrode via is formed within the opening.

Original Abstract Submitted

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.