US Patent Application 18364646. PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VOLTAGE DEVICES simplified abstract

PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VOLTAGE DEVICES

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Hung-Ling Shih of Tainan City (TW)

PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VOLTAGE DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18364646 titled 'PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VOLTAGE DEVICES

Simplified Explanation

- The patent application describes a method for forming a shallow trench isolation (STI) structure in a substrate. - The method involves forming a masking layer with an opening over the STI structure, and then removing portions of the STI structure, substrate, and masking layer. - An insulator liner layer is then formed within the substrate, and portions of it are removed from the lower surface of the substrate. - Finally, a semiconductor material is formed over the substrate and insulator liner layer. - The method aims to improve the isolation and performance of semiconductor devices.

Original Abstract Submitted

In some embodiments, the present disclosure relates to a method that includes forming a shallow trench isolation (STI) structure that extends into a substrate. A masking layer is formed over the substrate and includes an opening overlying the STI structure. A first removal process removes portions of the STI structure underlying the opening of the STI structure. A second removal process laterally removes portions of the substrate below the STI structure. A third removal process removes portions of the substrate that directly underlie the opening of the masking layer. An insulator liner layer is formed within inner surfaces of the substrate as defined by the first, second, and third removal processes. Further, a fourth removal process removes portions of the insulator liner layer covering a lower surface of the substrate. A semiconductor material is then formed over the SOI substrate and on the insulator liner layer.