US Patent Application 18364614. METHODS FOR REDUCING SCRATCH DEFECTS IN CHEMICAL MECHANICAL PLANARIZATION simplified abstract
Contents
METHODS FOR REDUCING SCRATCH DEFECTS IN CHEMICAL MECHANICAL PLANARIZATION
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Wan-Chun Pan of Hsinchu City (TW)
William Weilun Hong of Hsinchu City (TW)
Ying-Tsung Chen of Hsinchu City (TW)
METHODS FOR REDUCING SCRATCH DEFECTS IN CHEMICAL MECHANICAL PLANARIZATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18364614 titled 'METHODS FOR REDUCING SCRATCH DEFECTS IN CHEMICAL MECHANICAL PLANARIZATION
Simplified Explanation
- The patent application describes a method for forming a semiconductor device. - The method involves using a precursor with a substrate and protrusions, which are separated by trenches. - A first dielectric layer is deposited over the protrusions and fills the trenches. This dielectric layer has a specific hardness. - The first dielectric layer is then treated with an oxidizer. - A chemical mechanical planarization (CMP) process is performed on the first dielectric layer. - The purpose of this method is to improve the formation of a semiconductor device by providing a specific dielectric layer and optimizing its surface through treatment and planarization.
Original Abstract Submitted
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.
