US Patent Application 18362916. CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME simplified abstract

CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Seid Hadi Rasouli of Hsinchu (TW)]]

[[Category:Jerry Chang Jui Kao of Hsinchu (TW)]]

[[Category:Xiangdong Chen of Hsinchu (TW)]]

[[Category:Tzu-Ying Lin of Hsinchu (TW)]]

[[Category:Yung-Chen Chen of Hsinchu (TW)]]

[[Category:Hui-Zhong Zhuang of Hsinchu (TW)]]

[[Category:Chi-Lin Liu of Hsinchu (TW)]]

CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18362916 titled 'CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME

Simplified Explanation

The abstract describes a clock gating circuit that includes various components such as transistors and an input circuit. The circuit is designed to adjust a clock output signal based on an inverted clock input signal. Here are the key points:

• The clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor, and a first pull-up transistor.
• The input circuit sets a first control signal on a first node based on a first or second enable signal.
• The cross-coupled pair of transistors is connected between the first node and an output node.
• The first transistor is connected between the first and a second node.
• The first pull-up transistor has a first gate terminal, a first drain terminal, and a first source terminal.
• The first gate terminal receives an inverted clock input signal.
• The first drain terminal is connected to the second node and the first transistor.
• The first pull-up transistor adjusts a clock output signal based on the inverted clock input signal.

Original Abstract Submitted

A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.