US Patent Application 18362670. REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS simplified abstract
Contents
REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chien-Yuan Chen of Hsinchu (TW)
Cheng-Hung Lee of Hsinchu (TW)
Hung-Jen Liao of Hsin-Chu City (TW)
Kao-Cheng Lin of Taipei City (TW)
Wei-Min Chan of Sindian City (TW)
REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18362670 titled 'REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS
Simplified Explanation
- The patent application is about circuit devices, specifically integrated circuit devices. - These devices are constructed with combination circuits that include two or more cascading transistors. - The cascading transistors have multiple internal nodes, which are not connected to a common metal stripe in the metal layers. - This absence of connections reduces or eliminates the load on the internal nodes. - The transistors in the cascading transistors are independent of each other.
Original Abstract Submitted
Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
