US Patent Application 18361704. SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME simplified abstract
Contents
SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chih-Hao Wang of Hsinchu County (TW)
Shi Ning Ju of Hsinchu City (TW)
Jia-Chuan You of Taoyuan County (TW)
Kuo-Cheng Chiang of Hsinchu County (TW)
SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18361704 titled 'SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME
Simplified Explanation
- The patent application describes a method for fabricating a structure with two fins extending from a substrate. - The structure includes an isolation structure to separate the bottom portions of the fins, source/drain features over each fin, and a dielectric fin placed between the two fins and over the isolation structure. - A dummy gate stack is then added over the isolation structure, fins, and dielectric fin, followed by one or more dielectric layers on the sidewalls of the dummy gate stack. - The method involves removing the dummy gate stack to create a gate trench within the dielectric layers, exposing the dielectric fin in the trench. - The dielectric fin is then trimmed to reduce its width. - After the trimming, a high-k metal gate is formed in the gate trench.
Original Abstract Submitted
A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.
