US Patent Application 18361560. REDUCING RC DELAY IN SEMICONDUCTOR DEVICES simplified abstract

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REDUCING RC DELAY IN SEMICONDUCTOR DEVICES

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Gulbagh Singh of Tainan City (TW)

Kun-Tsang Chuang of Miaoli City (TW)

Po-Jen Wang of Taichung City (TW)

REDUCING RC DELAY IN SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18361560 titled 'REDUCING RC DELAY IN SEMICONDUCTOR DEVICES

Simplified Explanation

The patent application describes a method for reducing RC delay in devices that use radio frequency or would benefit from RC delay reduction.

  • The method involves creating a transistor structure on a substrate, with source/drain regions and a gate structure.
  • A first dielectric layer is deposited on the substrate to embed the transistor structure.
  • Source/drain contacts are formed within the first dielectric layer on the source/drain regions of the transistor structure.
  • A second dielectric layer is deposited on top of the first dielectric layer.
  • Metal lines are formed in the second dielectric layer.
  • An opening is created in the second dielectric layer between the metal lines to expose the first dielectric layer.
  • Through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts is etched.
  • A third dielectric layer is deposited to create an air-gap in the first and second dielectric layers and over the transistor structure.


Original Abstract Submitted

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

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