US Patent Application 18360118. Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells simplified abstract
Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Jhon Jhy Liaw of Hsinchu County (TW)
Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells - A simplified explanation of the abstract
This abstract first appeared for US patent application 18360118 titled 'Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells
Simplified Explanation
- This patent application describes an integrated circuit (IC) and its manufacturing method. - The IC includes different types of transistors, specifically gate-all-around (GAA) transistors and fin-like field effect transistors (FinFETs). - The IC has a first region where a first cell with one or more first type GAA transistors is located. - Adjacent to the first cell is a second cell with one or more second type GAA transistors, which are different from the first type. - The first type GAA transistors can be either nanosheet transistors or nanowire transistors, while the second type GAA transistors are the other one of the two. - The IC also has a second region where one or more FinFETs are located, and this region is separated from the first region by a distance. - The integration layout and manufacturing method of this IC are disclosed in the patent application.
Original Abstract Submitted
Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.
