US Patent Application 18359486. Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices simplified abstract
Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Shih-Kang Fu of Taoyuan County (TW)
Ming-Han Lee of Taipei City (TW)
Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 18359486 titled 'Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices
Simplified Explanation
The patent application describes a semiconductor structure with specific features and arrangements.
- The structure includes a contact on a substrate and an interlayer dielectric (ILD) layer.
- The ILD layer has two regions: a first region directly above the contact and a second region adjacent to the first region.
- The first region contains embedded first conductive features that are separated by a certain distance.
- A dielectric layer is embedded in the ILD layer and is located between the first conductive features in the first region.
- The second region does not have the dielectric layer and instead contains second conductive features that are separated by a greater distance than the first conductive features.
The innovation in this patent application is the specific arrangement and configuration of the semiconductor structure, which includes separate regions with different conductive features and distances between them.
Original Abstract Submitted
A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.
