US Patent Application 18356080. METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS simplified abstract
Contents
METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Ka-Hing Fung of Hsinchu County (TW)
METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18356080 titled 'METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS
Simplified Explanation
The patent application describes a method for forming gate spacers and an epitaxy source/drain structure in a semiconductor device.
- The method involves forming a gate stack over a fin of a substrate.
- Multiple dielectric layers are sequentially deposited over the gate stack, with the second dielectric layer having a lower dielectric constant than the first and third dielectric layers.
- A filling dielectric is also deposited over the gate stack.
- A dielectric cap is formed over the dielectric layers and the filling dielectric.
- The dielectric cap, dielectric layers, and filling dielectric are etched simultaneously to form gate spacers on the sidewalls of the gate stack and expose the top surface of the fin.
- After the gate spacers are formed, an epitaxy source/drain structure is formed in contact with one of the gate spacers and the top surface of the fin.
Original Abstract Submitted
A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.