US Patent Application 18335167. CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY simplified abstract
Contents
CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Rainer Yen-Chieh Huang of Changhua County (TW)
Hai-Ching Chen of Hsinchu City (TW)
Chung-Te Lin of Tainan City (TW)
CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18335167 Titled 'CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY'
Simplified Explanation
The abstract describes an integrated chip that has a gate electrode and a gate dielectric layer made of a ferroelectric material. There is also an active structure made of a semiconductor material, with a source contact and a drain contact arranged on top. A capping structure made of a first metal material is placed between the source and drain contacts and over the active structure.
Original Abstract Submitted
In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.
