US Patent Application 18303401. Built-in Self-Test for Die-to-Die Physical Interfaces simplified abstract

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Built-in Self-Test for Die-to-Die Physical Interfaces

Organization Name

Apple Inc.==Inventor(s)==

[[Category:Fabien S. Faure of Santa Clara CA (US)]]

[[Category:Arnaud J. Forestier of San Diego CA (US)]]

[[Category:Vikram Mehta of Cupertino CA (US)]]

Built-in Self-Test for Die-to-Die Physical Interfaces - A simplified explanation of the abstract

This abstract first appeared for US patent application 18303401 titled 'Built-in Self-Test for Die-to-Die Physical Interfaces

Simplified Explanation

The patent application describes a system that includes two integrated circuits and their respective interface circuits and test circuits.

  • The first integrated circuit has a transmit pin and a receive pin, along with a test circuit.
  • The second integrated circuit also has a transmit pin and a receive pin, along with a test circuit.
  • The second receive pin is connected to the first transmit pin, and the first receive pin is connected to the second transmit pin.
  • The second test circuit is designed to route signals from the second receive pin to the second transmit pin.
  • This allows a test signal sent from the first integrated circuit to be received by the second receive pin, bypass the second test circuit, and be routed to the second transmit pin.
  • The first test circuit is configured to receive this routed test signal on the first receive pin via the second conductive path.


Original Abstract Submitted

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

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