US Patent Application 18303219. FAULT DIAGNOSTICS simplified abstract

FAULT DIAGNOSTICS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Sandeep Kumar Goel of Dublin CA (US)

Ankita Patidar of San Jose CA (US)

FAULT DIAGNOSTICS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18303219 titled 'FAULT DIAGNOSTICS

Simplified Explanation

The patent application describes a process for identifying defects in cells of a circuit.

• The process starts by receiving a layout of the circuit, which includes a first cell and a second cell separated by a boundary circuit.
• The process then determines bridge pairs, which are pairs of boundary nodes from the first cell and the second cell.
• The next step is to model any faults that may occur between the bridge pairs.
• Finally, the process generates a test pattern to detect these bridge pair faults.

Bullet points:

• Process for identifying defects in cells of a circuit
• Receives a layout of the circuit with a first and second cell separated by a boundary circuit
• Determines bridge pairs by pairing boundary nodes from the first and second cell
• Models faults that may occur between the bridge pairs
• Generates a test pattern to detect these bridge pair faults

Original Abstract Submitted

Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.