US Patent Application 18233456. SEMICONDUCTOR DEVICE simplified abstract
Contents
SEMICONDUCTOR DEVICE
Organization Name
Semiconductor Energy Laboratory Co., Ltd.
Inventor(s)
Shunpei Yamazaki of Setagaya (JP)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18233456 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a new structure for a semiconductor device.
- The device includes a first transistor with a channel formation region on a substrate containing a semiconductor material.
- Impurity regions are formed with the channel formation region in between.
- A first gate insulating layer is placed over the channel formation region, followed by a first gate electrode.
- The first source electrode and first drain electrode are electrically connected to the impurity region.
- The device also includes a second transistor with a second gate electrode over the substrate containing a semiconductor material.
- A second gate insulating layer is placed over the second gate electrode, followed by an oxide semiconductor layer.
- The second source electrode and second drain electrode are electrically connected to the oxide semiconductor layer.
Original Abstract Submitted
An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
