US Patent Application 18232539. THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY simplified abstract

THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Meng-Sheng Chang of Chu-bei City (TW)]]

[[Category:Chia-En Huang of Xinfeng Township (TW)]]

[[Category:Yi-Ching Liu of Hsinchu City (TW)]]

[[Category:Yih Wang of Hsinchu City (TW)]]

THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232539 titled 'THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY

Simplified Explanation

- The patent application is related to a memory array that includes one-time programmable (OTP) cells. - The memory array consists of a first set of OTP cells that are connected between a first program control line and a first bit line. - Each OTP cell in the first set includes a programmable storage device and a switch that connects the first program control line to the first bit line. - The first program control line extends in a first direction towards one side of the memory array. - The first bit line extends in a second direction towards the opposite side of the memory array. - Each switch in the first set of OTP cells has a gate electrode that is connected to a corresponding read control line. - The read control lines extend in a second direction that crosses the first direction. - The innovation simplifies the structure and operation of OTP cells in a memory array. - The design allows for efficient programming and reading of data in the memory array. - The arrangement of the program control line, bit line, and read control line enables effective communication and control within the memory array.

Original Abstract Submitted

Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a first set of one-time programmable (OTP) cells connected between a first program control line and a first bit line. Each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first bit line. The first program control line extends towards a first side of the memory array along a first direction. The first bit line extends towards a second side of the memory array facing away from the first side of the memory array. Each switch of the first set of OTP cells includes a gate electrode coupled to a corresponding read control line extending along a second direction traversing the first direction.