US Patent Application 18232289. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Chia-Chi Yu of New Taipei City (TW)]]

[[Category:Jui Fu Hsieh of Zhubei City (TW)]]

[[Category:Yu-Li Lin of Kaohsiung City (TW)]]

[[Category:Chih-Teng Liao of Hsinchu City (TW)]]

[[Category:Yi-Jen Chen of Hsinchu City (TW)]]

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232289 titled 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Simplified Explanation

The patent application describes a method for forming a structure called a wall fin on semiconductor fins. The process involves multiple steps of forming and recessing dielectric layers and a fin liner layer, as well as forming source/drain epitaxial layers on the recessed semiconductor fins. The wall fin separates the source/drain epitaxial layers from each other.

• Method for forming a wall fin structure on semiconductor fins
• Multiple dielectric layers are formed and recessed to create the wall fin
• Fin liner layer is formed and recessed, along with the semiconductor fins
• Source/drain epitaxial layers are formed on the recessed semiconductor fins
• Wall fin separates the source/drain epitaxial layers from each other

Original Abstract Submitted

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.