US Patent Application 18232171. Semiconductor Device With Isolation Structures simplified abstract
Contents
Semiconductor Device With Isolation Structures
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Pang-Yen Tsai of Jhu-bei City (TW)
Tsungyu Hung of Hsinchu City (TW)
Huang-Lin Chao of Hillsboro OR (US)
Semiconductor Device With Isolation Structures - A simplified explanation of the abstract
This abstract first appeared for US patent application 18232171 titled 'Semiconductor Device With Isolation Structures
Simplified Explanation
The patent application describes a method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure.
- The method involves several steps to create the desired structure:
- An etch stop layer is formed on a substrate.
- A superlattice structure is formed on top of the etch stop layer.
- An isolation layer is deposited on the superlattice structure.
- A semiconductor layer is deposited on the isolation layer.
- A bi-layer isolation structure is formed on the semiconductor layer.
- The substrate and etch stop layer are removed.
- The superlattice structure, isolation layer, semiconductor layer, and bi-layer isolation structure are etched to form a fin structure.
- A gate-all-around structure is formed on the fin structure.
The innovation lies in the use of superlattice structures and an embedded isolation structure to create a semiconductor device.
Original Abstract Submitted
A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.
