US Patent Application 18231902. METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE simplified abstract
Contents
METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE
Organization Name
Semiconductor Energy Laboratory Co., Ltd.
Inventor(s)
Shunpei Yamazaki of Tokyo (JP)
Hiroki Ohara of Sagamihara (JP)
Toshinari Sasaki of Atsugi (JP)
Hideaki Kuwabara of Isehara (JP)
METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18231902 titled 'METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that aims to reduce parasitic capacitance between wirings.
- The device includes an oxide insulating layer that acts as a protective layer for the channel.
- The oxide insulating layer is formed over part of an oxide semiconductor layer that overlaps with a gate electrode layer.
- Additionally, in the same step, another oxide insulating layer is formed to cover the peripheral portion of the oxide semiconductor layer.
- The purpose of this second oxide insulating layer is to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer.
- By increasing this distance, the device is able to reduce parasitic capacitance.
Original Abstract Submitted
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
