US Patent Application 18231769. METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK simplified abstract
METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Yu-Der Chih of Hsin-Chu City (TW)
Chien-Yin Liu of Hsinchu City (TW)
METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK - A simplified explanation of the abstract
This abstract first appeared for US patent application 18231769 titled 'METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK
Simplified Explanation
The patent application describes a method and apparatus for improving the defect tolerability of a hardware-based neural network.
- The method involves performing calculations on the first neurons of a neural network's first layer.
- A first pattern of a memory cell array is received.
- A second pattern of the memory cell array is determined based on a third pattern.
- At least one pair of columns of the memory cell array is determined using the first pattern and the second pattern.
- Input data of two columns in each pair of columns of the memory cell array is switched.
- Output data of the two columns in each pair of columns of the memory cell array is switched to determine the values on the first neurons of the first layer.
Original Abstract Submitted
Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
