US Patent Application 18218243. QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME simplified abstract
QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
Hojun Yoon of Hwaseong-si (KR)
Wonjoo Jung of Bucheon-si (KR)
Youngchul Cho of Seongnam-si (KR)
Junghwan Choi of Hwaseong-si (KR)
QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18218243 Titled 'QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME'
Simplified Explanation
The abstract describes a circuit that corrects errors in the quadrature (phase and amplitude) of clock signals. It includes several components such as a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit.
The duty cycle adjusting circuit adjusts the skew (time difference) and duty cycle error of clock signals by delaying the edges of one clock signal and the falling edge of another clock signal. This adjustment is done based on control code sets.
The phase interpolator generates a delayed and selected clock signal by delaying a selected clock signal from the adjusted signals.
The phase detector detects the phase difference between two clock signals and generates an up/down signal.
The delay control circuit generates control code sets based on the up/down signal, which are then used by the duty cycle adjusting circuit to make further adjustments.
Original Abstract Submitted
A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.
