US Patent Application 18194249. INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING simplified abstract

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INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Niraj Nandan of PLANO TX (US)

Mihir Mody of Bangalore (IN)

Rajasekhar Allu of PLANO TX (US)

Manoj Koul of ALLEN TX (US)

Pandy Kalimuthu of PLANO TX (US)

David Stoller of PLANO TX (US)

INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18194249 titled 'INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING

Simplified Explanation

The patent application describes an integrated circuit that includes multiple image processing blocks, data selection circuitry, and a pipeline memory.

  • The integrated circuit has four image processing blocks, with each block receiving and processing image data.
  • The output of the first image processing block is connected to the input of the second image processing block, creating a sequential processing flow.
  • The output of the second image processing block is connected to the input of the third image processing block, continuing the sequential processing.
  • The data selection circuitry has two inputs, one connected to the output of the first image processing block and the other connected to the output of the second image processing block.
  • The data selection circuitry selects and outputs data from either the first or second image processing block.
  • The output of the data selection circuitry is connected to the input of the pipeline memory, which stores the selected data.
  • The output of the pipeline memory is connected to the input of the fourth image processing block, allowing further processing of the stored data.


Original Abstract Submitted

In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

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