US Patent Application 18187971. METHOD AND APPARATUS WITH REPEATED MULTIPLICATION simplified abstract

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METHOD AND APPARATUS WITH REPEATED MULTIPLICATION

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Ho Young Kim of Suwon-si (KR)]]

[[Category:Won Woo Ro of Seoul (KR)]]

[[Category:Se Hyun Yang of Suwon-si (KR)]]

[[Category:Dong Ho Ha of Seoul (KR)]]

METHOD AND APPARATUS WITH REPEATED MULTIPLICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18187971 titled 'METHOD AND APPARATUS WITH REPEATED MULTIPLICATION

Simplified Explanation

The patent application describes a processing device that includes a calculator and a buffer for storing calculation rules and operands.

  • The processing device has a first buffer that stores calculation rules and a second buffer that stores operands.
  • The calculator includes multiple multipliers and an adder.
  • The multipliers are designed to perform repeated multiplication.
  • The second buffer enqueues the operands into a queue based on the calculation rules.
  • The counter keeps track of the number of times each multiplier needs to perform multiplication.
  • Each multiplier provides a non-final multiplication result to a first path if the number of multiplications performed is less than the specified number.
  • Each multiplier provides a final multiplication result to a second path if the number of multiplications performed is equal to the specified number.


Original Abstract Submitted

A processing device including a first buffer storing calculation rules, a calculator including a plurality of multipliers and an adder, the multipliers configured to perform multiplication repeatedly, a second buffer storing operands, the second buffer being configured to enqueue the operands based on the calculation rules into a queue, and a counter indicating a respective number indicating a number of times a multiplication is to be performed by each of the plurality of multipliers, each multiplier of the plurality of multipliers being configured to provide a non-final multiplication result to a first path to an input of the corresponding multiplier responsive to a corresponding number of multiplications performed by the multiplier being less than the respective number, and provide a final multiplication result to a second path to the adder responsive to the corresponding number of multiplications performed by the multiplier being equal to the respective number.

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