US Patent Application 18153312. REFRESH ADDRESS GENERATION CIRCUIT simplified abstract

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REFRESH ADDRESS GENERATION CIRCUIT

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Yinchuan Gu of Hefei City (CN)

REFRESH ADDRESS GENERATION CIRCUIT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18153312 titled 'REFRESH ADDRESS GENERATION CIRCUIT

Simplified Explanation

The patent application describes a circuit for generating refresh addresses.

  • The circuit includes a refresh control circuit and an address generator.
  • The refresh control circuit receives multiple refresh commands and performs corresponding refresh operations.
  • It outputs a first clock signal when the number of refresh operations is less than m, and a second clock signal when the number of refresh operations is equal to m.
  • The address generator is connected to the refresh control circuit and stores a first address.
  • It receives the first or second clock signal and outputs an address to be refreshed during each refresh operation.
  • The first address is changed in response to the second clock signal.
  • The address to be refreshed includes the first address and a second address with the lowest bit opposite to that of the first address.


Original Abstract Submitted

A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

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