US Patent Application 18152492. Reference Clock Switching in Phase-Locked Loop Circuits simplified abstract

Reference Clock Switching in Phase-Locked Loop Circuits

Organization Name

Apple Inc.

Inventor(s)

Hairong Yu of Saratoga CA (US)

Boon-Aik Ang of Los Altos CA (US)

Yu Chen of Santa Clara CA (US)

Litesh Sajnani of Santa Clara CA (US)

Samed Maltabas of Santa Clara CA (US)

Shaobo Liu of Sunnyvale CA (US)

Gregory N. Santos of Melbourne FL (US)

Richard Y. Su of Santa Clara CA (US)

Meei-Ling Chiang of Cupertino CA (US)

Pyoungwon Park of San Jose CA (US)

Dennis M. Fischette, Jr. of Mountain View CA (US)

Reference Clock Switching in Phase-Locked Loop Circuits - A simplified explanation of the abstract

This abstract first appeared for US patent application 18152492 titled 'Reference Clock Switching in Phase-Locked Loop Circuits

Simplified Explanation

The patent application describes a clock generator circuit that includes a multiplex circuit and a phase-locked loop circuit.

• The multiplex circuit generates a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals.
• When the reference clock signal is switched from one clock signal to another, the phase-locked loop circuit disables phase-locking and enters a frequency acquisition mode.
• During the frequency acquisition mode, the phase-locked loop circuit adjusts the frequency of its output clock signal based on the frequency of the newly selected reference clock signal.
• After a certain period of time, the phase-locked loop circuit returns to phase-locking operation.

Original Abstract Submitted

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.