US Patent Application 18140985. SEMICONDUCTOR PACKAGE simplified abstract

SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:JIWON Shin of Daejeon (KR)]]

[[Category:DONGUK Kwon of Asan-si (KR)]]

[[Category:KWANG BOK Woo of Cheonan-si (KR)]]

[[Category:MINSEUNG Ji of Seoul (KR)]]

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18140985 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package that includes two sub-semiconductor devices stacked on top of each other, with a heat sink covering the top device.

• The package consists of a first sub-semiconductor device with a substrate and a chip, an interposer, and a second sub-semiconductor device.
• The interposer has a dielectric layer, a thermal conductive layer, a first thermal conductive pad, and thermal conductive vias.
• The thermal conductive layer is in contact with the bottom surface of the dielectric layer and is connected to the top surface of the first semiconductor chip.
• The second sub-semiconductor device is placed on the dielectric layer without overlapping the first thermal conductive pad.
• The heat sink covers the second sub-semiconductor device and is connected to the first thermal conductive pad.

Original Abstract Submitted

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.