US Patent Application 18062853. ANALOG-TO-DIGITAL CONVERTING CIRCUIT FOR DECREASING DECISION DELAY AND OPERATION METHOD THEREOF simplified abstract

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ANALOG-TO-DIGITAL CONVERTING CIRCUIT FOR DECREASING DECISION DELAY AND OPERATION METHOD THEREOF

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Daehwa Paik of Suwon-si (KR)


Cyuyeol Rhee of Suwon-si (KR)


Kyungil Kim of Suwon-si (KR)


Jaehong Kim of Suwon-si (KR)


Jinwoo Kim of Suwon-si (KR)


Seunghyun Lim of Suwon-si (KR)


Sanghyun Cho of Suwon-si (KR)


ANALOG-TO-DIGITAL CONVERTING CIRCUIT FOR DECREASING DECISION DELAY AND OPERATION METHOD THEREOF - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18062853 Titled 'ANALOG-TO-DIGITAL CONVERTING CIRCUIT FOR DECREASING DECISION DELAY AND OPERATION METHOD THEREOF'

Simplified Explanation

The abstract describes a circuit that converts analog signals to digital signals. It consists of two amplifiers. The first amplifier compares a signal from a pixel array with a ramp signal and produces an output signal. The second amplifier generates a second output signal based on the first output signal. It includes several components such as transistors, a capacitor, and a current source. These components work together to provide power supply voltage, control the turning on and off of certain elements, and generate a power current.


Original Abstract Submitted

An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.