US Patent Application 18031070. Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor simplified abstract
Contents
Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor
Organization Name
Telefonaktiebolaget LM Ericsson (publ)
Inventor(s)
Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor - A simplified explanation of the abstract
This abstract first appeared for US patent application 18031070 titled 'Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor
Simplified Explanation
- The patent application describes techniques for detecting and resolving resource monopolization in a microprocessor that supports Simultaneous Multi-Threading (SMT). - The techniques involve updating thread rankings on an instruction cycle basis, from slowest to fastest. - Instructions from slower threads are redirected to bypass shared resources that would otherwise be monopolized by these slower threads. - Bypassing includes redirecting selected instructions to lower-cost or lower-power secondary resources, such as bypassing an instruction queue in favor of a less complex buffer circuit.
Original Abstract Submitted
Techniques disclosed herein provide, among other things, advantageous mechanisms for detecting and resolving resource monopolization by one or more “slower” instruction threads in an instruction pipeline of a microprocessor that supports Simultaneous Multi-Threading (SMT). One or more embodiments involve updating thread rankings, e.g., from slowest to fastest, on an instruction cycle basis, and redirecting instructions from at least a slowest one of the threads, to bypass one or more shared resources that would otherwise be monopolized by instructions in the slower/slowest threads. In at least one embodiment, bypassing includes redirecting selected instructions away from more critical shared resources to lower-cost or lower-power secondary resources, for example bypassing an instruction queue in favor of a less complex buffer circuit.
