US Patent Application 17994175. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE simplified abstract

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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:KEUNNAM Kim of SUWON-SI (KR)]]

[[Category:KISEOK Lee of SUWON-SI (KR)]]

[[Category:BYEONGJOO Ku of SUWON-SI (KR)]]

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17994175 titled 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE

Simplified Explanation

The patent application describes a semiconductor memory device with specific components and features.

  • The device includes a substrate and an insulating layer on the substrate.
  • There are first and second peripheral active regions on the insulating layer, each with a first and second surface.
  • A device isolation layer is present between the first and second peripheral active regions to isolate them.
  • A bit line is connected to either the first surface of the first peripheral active region or the first surface of the second peripheral active region.
  • A first gate insulating layer is provided on the second surfaces of the first and second peripheral active regions.
  • A first peripheral gate electrode is placed on the first gate insulating layer, and a second peripheral gate electrode is placed on the second gate insulating layer.
  • A contact pattern is connected to the bit line.
  • Each of the first and second peripheral active regions is floated in relation to the substrate by the insulating layer.


Original Abstract Submitted

A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.

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