US Patent Application 17964677. 3D-STACKED SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FORMED OF POLYCRYSTALLINE SILICON OR POLYCRYSTALLINE SILICON INCLUDING DOPANTS simplified abstract
3D-STACKED SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FORMED OF POLYCRYSTALLINE SILICON OR POLYCRYSTALLINE SILICON INCLUDING DOPANTS
Organization Name
Inventor(s)
Seungchan Yun of Waterford NY (US)
Jaejik Baek of Watervliet NY (US)
Gunho Jo of Schenectady NY (US)
Byounghak Hong of Latham NY (US)
Kang-ill Seo of Latham NY (US)
3D-STACKED SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FORMED OF POLYCRYSTALLINE SILICON OR POLYCRYSTALLINE SILICON INCLUDING DOPANTS - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17964677 Titled '3D-STACKED SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FORMED OF POLYCRYSTALLINE SILICON OR POLYCRYSTALLINE SILICON INCLUDING DOPANTS'
Simplified Explanation
The abstract describes a multi-stack semiconductor device that consists of a substrate, a lower field-effect transistor, and an upper field-effect transistor. The lower field-effect transistor has a lower channel structure surrounded by a lower gate structure, which includes a lower work-function metal layer and a lower gate electrode. Similarly, the upper field-effect transistor has an upper channel structure surrounded by an upper gate structure, which includes an upper work-function metal layer and an upper gate electrode. Both the lower and upper gate electrodes are made of a metal or a metal compound. The lower gate electrode is composed of polycrystalline silicon (poly-Si) or poly-Si with a dopant, while the upper gate electrode is made of a metal or a metal compound.
Original Abstract Submitted
Provided is a multi-stack semiconductor device that includes: a substrate; a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work-function metal layer and a lower gate electrode; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper work-function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode includes a metal or a metal compound, and wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si comprising a dopant, and the upper gate electrode comprises a metal or a metal compound.
