US Patent Application 17864192. PLANE BALANCING IN A MEMORY SYSTEM simplified abstract
Contents
PLANE BALANCING IN A MEMORY SYSTEM
Organization Name
Inventor(s)
John J. Kane of Westminster CO (US)
Byron D. Harris of Mead CO (US)
Vivek Shivhare of Milpitas CA (US)
PLANE BALANCING IN A MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 17864192 titled 'PLANE BALANCING IN A MEMORY SYSTEM
Simplified Explanation
Methods, systems, and devices for plane balancing in a memory system are described in this patent application. The memory system selects a memory die to write a set of data, which consists of a plurality of planes, each containing multiple blocks of memory cells. The memory system determines the availability status of blocks in two different planes and writes the set of data to the planes, excluding the first plane, based on the quantity of available blocks in each plane.
- The patent application focuses on plane balancing in a memory system.
- The memory system selects a memory die for writing a set of data.
- The memory die consists of multiple planes, each containing blocks of memory cells.
- The memory system determines the availability status of blocks in two different planes.
- The set of data is written to the planes, excluding the first plane.
- The decision of which planes to write the data to is based on the quantity of available blocks in each plane.
Potential applications of this technology include:
- Improving the performance and efficiency of memory systems.
- Enhancing the reliability and lifespan of memory devices.
- Optimizing data storage and retrieval processes in memory systems.
- Enabling better management of memory resources in various applications, such as computer systems, mobile devices, and data centers.
Original Abstract Submitted
Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.
